Basic interrupts are working.

2 files changed, 181 insertions, 0 deletions

diff --git a/fdl/ch573/pfic.fdl b/fdl/ch573/pfic.fdl
new file mode 100644
index 0000000..13ed54f
--- /dev/null
+++ b/fdl/ch573/pfic.fdl
@@ -0,0 +1,109 @@
+import "ch573/common.fdl";
+
+/** Fiddle file for the Programmable Fast Interrupt Controller (PFIC) */
+package ch573.pfic {
+  location pfic_base = 0xE000E000;
+
+  using ch573.common;
+
+  bits interrupts : enum(32) {
+    [[ c: unqualified ]]
+    IRQ_SysTick = 0x1000,
+  };
+
+  /** Type definition for the PFIC structure */
+  type pfic_t : struct {
+    /** PFIC interrupt enable status register */
+    reg interrupt_enable_status(64) @0x00 : struct {
+      intensta_low : (32);  // Interrupt enable status for interrupts 31:0
+      intensta_high : (32); // Interrupt enable status for interrupts 63:32
+    };
+
+    /** PFIC interrupt suspension status register */
+    reg interrupt_suspension_status(64) @0x20 : struct {
+      pendsta_low : (32);  // Interrupt suspension status for interrupts 31:0
+      pendsta_high : (32); // Interrupt suspension status for interrupts 63:32
+    };
+
+    /** PFIC interrupt priority threshold configuration register */
+    reg interrupt_priority_threshold(32) @0x40 : struct {
+      threshold : (8);  // Priority threshold setting
+      reserved(24);
+    };
+
+    /** PFIC fast interrupt service base address registers */
+    reg fast_interrupt_base_address(64) : struct {
+      irqid0 : (8);  // IRQ ID for fast interrupt 0
+      offset0 : (24); // Offset address for fast interrupt 0
+      irqid1 : (8);  // IRQ ID for fast interrupt 1
+      offset1 : (24); // Offset address for fast interrupt 1
+    };
+
+    reg fast_interrupt_base_address_2(64) : struct {
+      irqid2 : (8);  // IRQ ID for fast interrupt 2
+      offset2 : (24); // Offset address for fast interrupt 2
+      irqid3 : (8);  // IRQ ID for fast interrupt 3
+      offset3 : (24); // Offset address for fast interrupt 3
+    };
+
+    /** PFIC interrupt enable register */
+    reg interrupt_enable(64) @0x100 : struct {
+      enable_low : (32);  // Enable for interrupts 31:0
+      enable_high : (32); // Enable for interrupts 63:32
+    };
+
+    /** PFIC interrupt disable register */
+    reg interrupt_disable(64) : struct {
+      disable_low : (32);  // Disable for interrupts 31:0
+      disable_high : (32); // Disable for interrupts 63:32
+    };
+
+    /** PFIC interrupt pending set register */
+    reg interrupt_pending_set(64) : struct {
+      pendset_low : (32);  // Pending set for interrupts 31:0
+      pendset_high : (32); // Pending set for interrupts 63:32
+    };
+
+    /** PFIC interrupt pending clear register */
+    reg interrupt_pending_clear(64) : struct {
+      pendreset_low : (32);  // Pending clear for interrupts 31:0
+      pendreset_high : (32); // Pending clear for interrupts 63:32
+    };
+
+    /** PFIC interrupt activation status register */
+    reg interrupt_active_status(64) : struct {
+      active_low : (32);  // Active status for interrupts 31:0
+      active_high : (32); // Active status for interrupts 63:32
+    };
+
+    /** PFIC interrupt priority configuration registers (IPRIORx) */
+    reg interrupt_priority_config(64) : struct {
+      priority_0_to_3 : (8);  // Priority for interrupts 0-3
+      priority_4_to_7 : (8);  // Priority for interrupts 4-7
+      priority_8_to_11 : (8); // Priority for interrupts 8-11
+      priority_12_to_15 : (8); // Priority for interrupts 12-15
+      priority_16_to_19 : (8); // Priority for interrupts 16-19
+      priority_20_to_23 : (8); // Priority for interrupts 20-23
+      priority_24_to_27 : (8); // Priority for interrupts 24-27
+      priority_28_to_31 : (8); // Priority for interrupts 28-31
+    };
+
+    /** PFIC system control register */
+    reg system_control(32) : struct {
+      hwstkctrl : bit_t;  // Hardware stack enable control
+      nestctrl  : bit_t;  // Nesting interrupt control
+      sleepdeep : bit_t;  // Low power consumption control
+      reserved(29);
+    };
+
+    /** PFIC vector table control register */
+    reg vector_table_control(32) : struct {
+      offset : bit_t;  // Offset vector table address
+      reserved(31);
+    };
+  };
+
+  /** Define an instance of the PFIC at the base address */
+  instance pfic at pfic_base : pfic_t;
+};
+
diff --git a/fdl/ch573/systick.fdl b/fdl/ch573/systick.fdl
new file mode 100644
index 0000000..8e05685
--- /dev/null
+++ b/fdl/ch573/systick.fdl
@@ -0,0 +1,72 @@
+import "ch573/common.fdl";
+
+/** Package for SYSTICK (system counter). */
+package ch573.systick {
+  location systick_base = 0xE000F000;
+
+  using ch573.common;
+
+  type systick_t : struct {
+    reg cfg(32) @0x0 : struct {
+      /** Enable the systick. */
+      rw enabled : enable_t;
+
+      /** Enable the systick interrupt. */
+      rw interrupt_enable : enable_t;
+
+      /** Clock source for the systick. */
+      rw clock_source : enum(1) {
+        [[ c: unqualified ]]
+        SYSTICK_CLOCK_SOURCE_HCLK = 1,
+
+        [[ c: unqualified ]]
+        SYSTICK_CLOCK_SOURCE_HCLK_DIV_8 = 0,
+      };
+
+      reserved(5);
+
+      /** Write 1 to reload the systick. */
+      wo st_reload : (1);
+      reserved(23);
+    };
+
+    assert_pos(0x4);
+    union {
+      struct {
+        /** Lower 32 bits of the systick count. */
+        reg count_low(32);
+        assert_pos(0x8);
+
+        /** Upper 32 bits of the systick count. */
+        reg count_high(32);
+      };
+      /** Full 64 bits of the systick count. */
+      reg count(64);
+    };
+
+    assert_pos(0xC);
+    union {
+      struct {
+        /** Lower 32 bits of the systick reload value. */
+        reg reload_low(32);
+        assert_pos(0x10);
+        /** Upper 32 bits of the systick reload value. */
+        reg reload_high(32);
+      };
+      /** Full 64-bit systick reload value. */
+      reg reload(64);
+    };
+
+    reg (32) @0x14 : struct {
+      /** Software interrupt happened. (Set to 1 to trigger a software
+       * interrupt.) */
+      software_interrupt_flag : (1);
+
+      /** Counter interrupt happened. */
+      counter_interrupt_flag : (1);
+      reserved(30);
+    };
+  };
+
+  instance systick at systick_base : systick_t;
+};