diff options
| author | Josh Rahm <joshuarahm@gmail.com> | 2024-11-15 02:48:27 -0700 |
|---|---|---|
| committer | Josh Rahm <joshuarahm@gmail.com> | 2024-11-15 02:48:27 -0700 |
| commit | ede9bee7f22fd5d0e1bacb7689f1cac23992b70b (patch) | |
| tree | 904d8d80063aa415b9e407f6ec73aa874483ebcd /fdl | |
| parent | 63054d2fdf9a0ae3e9dcdd0d20eb8714671a010b (diff) | |
| download | ch573-ede9bee7f22fd5d0e1bacb7689f1cac23992b70b.tar.gz ch573-ede9bee7f22fd5d0e1bacb7689f1cac23992b70b.tar.bz2 ch573-ede9bee7f22fd5d0e1bacb7689f1cac23992b70b.zip | |
UART is working.
Diffstat (limited to 'fdl')
| -rw-r--r-- | fdl/ch573/gpio.fdl | 10 | ||||
| -rw-r--r-- | fdl/ch573/pwr.fdl | 28 | ||||
| -rw-r--r-- | fdl/ch573/uart.fdl | 11 |
3 files changed, 46 insertions, 3 deletions
diff --git a/fdl/ch573/gpio.fdl b/fdl/ch573/gpio.fdl index c54d956..bab481a 100644 --- a/fdl/ch573/gpio.fdl +++ b/fdl/ch573/gpio.fdl @@ -34,7 +34,10 @@ package ch573.gpio { }; /** Pin input register. */ - reg pin(32); + reg pin(32) : struct { + in : bit_t[16]; + reserved(16); + }; /** Pin output register. */ reg (32) : struct { @@ -46,7 +49,10 @@ package ch573.gpio { reg clr(32); /** Pull-up resistor configuration. */ - reg pu(32); + reg (32) : struct { + pu : enable_t[16]; + reserved(16); + }; /** pull-down/drive configuration register. */ reg (32) : struct { diff --git a/fdl/ch573/pwr.fdl b/fdl/ch573/pwr.fdl new file mode 100644 index 0000000..65f2dbb --- /dev/null +++ b/fdl/ch573/pwr.fdl @@ -0,0 +1,28 @@ +import "ch573/common.fdl"; + +/** Package for the system power control registers. */ +package ch573.pwr { + location pwr_base = 0x4000100C; + + bits clock_source_status_t : enum(1) { + [[ c: unqualified ]] + CLK_SOURCE_ENABLED = 0, + [[ c: unqualified ]] + CLK_SOURCE_DISABLED = 1, + }; + + type pwr_mgmt_t : struct { + reg slp_clk_off_0(8) : struct { + tmr0 : clock_source_status_t; + tmr1 : clock_source_status_t; + tmr2 : clock_source_status_t; + tmr3 : clock_source_status_t; + uart0 : clock_source_status_t; + uart1 : clock_source_status_t; + uart2 : clock_source_status_t; + uart3 : clock_source_status_t; + }; + }; + + instance pwr_mgmt at pwr_base : pwr_mgmt_t; +}; diff --git a/fdl/ch573/uart.fdl b/fdl/ch573/uart.fdl index bc2df2d..9a4f0c5 100644 --- a/fdl/ch573/uart.fdl +++ b/fdl/ch573/uart.fdl @@ -70,7 +70,16 @@ package ch573.uart { /** Line Control Register */ reg lcr(8) : struct { /** UART word size (5-8 bits) */ - word_sz : (2); + word_sz : enum(2) { + [[ c: unqualified ]] + WORD_SZ_5_BITS = 0b00, + [[ c: unqualified ]] + WORD_SZ_6_BITS = 0b01, + [[ c: unqualified ]] + WORD_SZ_7_BITS = 0b10, + [[ c: unqualified ]] + WORD_SZ_8_BITS = 0b11, + }; /** Stop bit setting */ stop_bit : bit_t; /** Parity bit enable */ |