Some SPI is working, a bit. Still no clock, but I'm about to give up on that.

1 files changed, 23 insertions, 8 deletions

diff --git a/fdl/ch573/spi.fdl b/fdl/ch573/spi.fdl
index 855d17f..cec88f3 100644
--- a/fdl/ch573/spi.fdl
+++ b/fdl/ch573/spi.fdl
@@ -8,6 +8,7 @@ package ch573.spi {
   using ch573.common;
 
   type spi_t : struct {
+    assert_pos(0x0);
     /** SPI0 Control Mode Register */
     reg ctrl_mod(8) : struct {
       /** SPI master/slave mode select */
@@ -18,18 +19,32 @@ package ch573.spi {
       wire_2_mod     : bit_t;
       union {
         /** Clock idle mode select in master mode */
-        mst_sck_mod  : bit_t;
+        mst_sck_mod  : enum(1) {
+          [[ c: unqualified ]]
+          CLOCK_IDLE_LOW = 0,
+
+          [[ c: unqualified ]]
+          CLOCK_IDLE_HIGH = 1,
+        };
         /** First byte command mode select in slave mode */
         slv_cmd_mod  : bit_t;
       };
       /** FIFO direction setting bit */
-      fifo_dir       : bit_t;
-      /** SCK output enable bit */
-      sck_oe         : bit_t;
-      /** MOSI output enable bit */
-      mosi_oe        : bit_t;
-      /** MISO output enable bit */
-      miso_oe        : bit_t;
+      fifo_dir : enum(1) {
+        [[ c: unqualified ]]
+        FIFO_DIR_INPUT = 1,
+
+        [[ c: unqualified ]]
+        FIFO_DIR_OUTPUT = 0,
+      };
+      struct {
+        /** SCK output enable bit */
+        sck_oe         : enable_t;
+        /** MOSI output enable bit */
+        mosi_oe        : enable_t;
+        /** MISO output enable bit */
+        miso_oe        : enable_t;
+      } pin_enable;
     };
 
     /** SPI0 Control Configuration Register */