1 files changed, 45 insertions, 0 deletions
diff --git a/include/risc-v.h b/include/risc-v.h
new file mode 100644
index 0000000..946ca7c
--- /dev/null
+++ b/include/risc-v.h
@@ -0,0 +1,45 @@
+#pragma once
+
+#include <stdint.h>
+
+/* Macros and functions for generic RISC-V cores. */
+
+/* Wait for interrupt macro. */
+static inline void wfi()
+{
+  asm volatile("wfi");
+}
+
+/* The mode for the mtvec. */
+typedef enum {
+  MODE_DIRECT = 0,
+  MODE_VECTORED = 1,
+} mtvec_mode_t;
+
+/* Macro to read the value from a RISC-V CSR. */
+#define csrr(csr)                                   \
+  ({                                                \
+    uint32_t _tmp_csr;                              \
+    asm volatile("csrr %0, " csr : "=r"(_tmp_csr)); \
+    _tmp_csr;                                       \
+  })
+
+/* Macro to write a value to a RISC-V CSR. */
+#define csrw(csr, v)                             \
+  {                                              \
+    asm volatile("csrw " csr ", %0" : : "r"(v)); \
+  }
+
+/* Sets the mtvec to point to the given vector_table with the given mode. */
+static inline void set_mtvec(void* vector_table, mtvec_mode_t mode)
+{
+  uint32_t mtvec = (uint32_t)vector_table;
+  mtvec |= !!mode;
+  csrw("mtvec", mtvec);
+}
+
+#define MCAUSE csrr("mcause")
+#define MEPC csrr("mepc")
+#define MTVAL csrr("mtval")
+
+#define __nop() asm volatile ("nop")