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import "ch573/common.fdl";
/** Package for the system clock registers. */
package ch573.clock {
location clock_base = 0x4000_1000;
using ch573.common;
type clock_cfg_t : struct {
skip_to(0x08);
assert_pos(0x08);
/** System clock configuration register */
reg clk_sys_cfg(16) : struct {
clk_pll_div : (5);
reserved(1);
/** The system clock source. */
clk_sys_mod : enum(2) {
/** 32 Mhz external clock source. */
[[ c: unqualified ]]
HCLK_SRC_CK32M = 0b00,
/** PLL clock source.*/
[[ c: unqualified ]]
HCLK_SRC_PLL = 0b01,
/** 32kHz internal clock. */
[[ c: unqualified ]]
HCLK_SRC_CK32K = 0b11,
reserved = 0b10,
};
reserved(8);
};
assert_pos(0x0A);
/** High frequency clock module power control register */
reg hfck_pwr_ctrl(8) : struct {
reserved(2);
/** External oscillator on. */
clk_xt32m_pon : bit_t;
reserved(1);
/** PLL Power on */
clk_pll_pon : bit_t;
reserved(3);
};
skip_to(0x2C);
assert_pos(0x2C);
/** Internal 32KHz clock tune register */
reg(16) : struct {
int32k_tune : (12);
reserved(4);
};
assert_pos(0x2E);
/** External 32KHz clock resonance tune register */
reg xt32k_tune(8) : struct {
reserved(4);
xt32k_c_load : (4);
};
assert_pos(0x2F);
/** 32KHz oscillator configuration register */
reg ck32k_config(8) : struct {
clk_int32k_pon : enable_t;
clk_xt32k_pon : enable_t;
clk_osc32k_xt : enum(1) {
[[ c: unqualified ]]
INTERNAL_32K_OSC = 1,
[[ c: unqualified ]]
EXTERNAL_32K_OSC = 0,
};
reserved(4);
rb_32k_clk_pin : enable_t;
};
assert_pos(0x30);
/** RTC flag and control register */
reg rtc_flag_ctrl(8) : struct {
reserved(4);
rtc_tmr_clr : bit_t;
rtc_trig_clr : bit_t;
ro rtc_tmr_flag : bit_t;
ro rtc_trig_flag : bit_t;
};
assert_pos(0x31);
/** RTC mode configuration register */
reg rtc_mode_ctrl(8) : struct {
rtc_tmr_mode : enum(3) {
[[ c: unqualified ]]
TMR_MODE_0_125_S = 0,
[[ c: unqualified ]]
TMR_MODE_0_25_S = 1,
[[ c: unqualified ]]
TMR_MODE_0_5_S = 2,
[[ c: unqualified ]]
TMR_MODE_1_S = 3,
[[ c: unqualified ]]
TMR_MODE_2_S = 4,
[[ c: unqualified ]]
TMR_MODE_4_S = 5,
[[ c: unqualified ]]
TMR_MODE_8_S = 6,
[[ c: unqualified ]]
TMR_MODE_16_S = 7,
};
/** Ignore and compare the lowest bit of matching value in trigger mode: */
rtc_ignore_b0 : enum(1) {
[[ c: unqualified ]]
IGNORE_LOWEST_BIT = 1,
[[ c: unqualified ]]
COMPARE_LOWEST_BIT = 0,
};
/** Rtc Timing mode enabled. */
rtc_tmr_en : enable_t;
/** Rtc trigger mode enabled. */
rtc_trig_en : enable_t;
/** Write 1 to load the low word of RTC counter, and automatically cleared
* after loading. Load the high 16 bits of R32_RTC_TRIG to R16_RTC_CNT_2S;
* load the low 16 bits of R32_RTC_TRIG to R16_RTC_CNT_32K */
rtc_load_lo : enable_t;
/** Write 1 to load the high word of RTC counter, and automatically cleared
* to 0 after loading. Load R32_RTC_TRIG (actually only the low 14 bits) to
* R32_RTC_CNT_DAY. */
rtc_load_hi : enable_t;
};
skip_to(0x34);
assert_pos(0x34);
/** RTC trigger value register */
reg rtc_trig(32);
assert_pos(0x38);
/** RTC based 32768Hz count value register */
reg rtc_cnt_32k(16);
assert_pos(0x3A);
/** RTC count value register in the unit of 2S */
reg rtc_cnt_2s(16);
assert_pos(0x3C);
/** RTC count value register in the unit of day */
reg (32) : struct {
rtc_cnt_day : (14);
reserved(18);
};
skip_to(0x4B);
assert_pos(0x4B);
/** PLL configuration register */
reg pll_config(8) : struct {
pll_config_dat : (7);
reserved(1);
};
skip_to(0x4E);
assert_pos(0x4E);
/** External 32MHz clock resonance tune register */
reg xt32m_tune(8) : struct {
/** External 32MHz oscillator bias current */
xt32m_i_bias : enum (2) {
/** 75% of rated current */
[[ c: unqualified ]]
CURRENT_75 = 0,
/** 100% of rated current */
[[ c: unqualified ]]
CURRENT_RATED = 1,
/** 125% of rated current */
[[ c: unqualified ]]
CURRENT_125 = 2,
/** 150% of rated current */
[[ c: unqualified ]]
CURRENT_150 = 3,
};
reserved(2);
/** Select the built-in load capacitor that matches the external 32MHz
* crystal (which may affect wireless communication): Capacity =
* RB_XT32M_C_LOAD * 2 + 10pF, 000b-111b correspond to approximately
* 10pF-24pF respectively. Choose according to the parameters of crystal
* used; the common value is 111b. */
xt32m_c_load : (3);
reserved(1);
};
reserved(8);
assert_pos(0x50);
/** Oscillator frequency calibration count value register */
reg(16) : struct {
osc_cal_cnt : (14);
reserved(2);
};
assert_pos(0x52);
/** Oscillator frequency calibration control register */
reg osc_cal_ctrl(8) : struct {
osc_cnt_en : bit_t;
osc_cnt_halt : bit_t;
reserved(6);
};
};
instance clock_cfg at clock_base : clock_cfg_t;
};
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