fdl/ch573/pwr.fdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

import "ch573/common.fdl";

/** Package for the system power control registers. */
package ch573.pwr {
  location pwr_base = 0x4000100C;

  bits clock_source_status_t : enum(1) {
    [[ c: unqualified ]]
    CLK_SOURCE_ENABLED = 0,
    [[ c: unqualified ]]
    CLK_SOURCE_DISABLED = 1,
  };

  type pwr_mgmt_t : struct {
    reg slp_clk_off_0(8) : struct {
      tmr0 : clock_source_status_t;
      tmr1 : clock_source_status_t;
      tmr2 : clock_source_status_t;
      tmr3 : clock_source_status_t;
      uart0 : clock_source_status_t;
      uart1 : clock_source_status_t;
      uart2 : clock_source_status_t;
      uart3 : clock_source_status_t;
    };
  };

  instance pwr_mgmt at pwr_base : pwr_mgmt_t;
};