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import "ch573/common.fdl";
/** Package for the SPI subsystem. */
package ch573.spi {
location spi_base = 0x4000_4000;
using ch573.common;
type spi_t : struct {
assert_pos(0x0);
/** SPI0 Control Mode Register */
reg ctrl_mod(8) : struct {
/** SPI master/slave mode select */
mode_slave : bit_t;
/** Clear FIFO/counter/interrupt flag */
all_clear : bit_t;
/** 2-wire/3-wire SPI mode select in slave mode */
wire_2_mod : bit_t;
union {
/** Clock idle mode select in master mode */
mst_sck_mod : enum(1) {
[[ c: unqualified ]]
CLOCK_IDLE_LOW = 0,
[[ c: unqualified ]]
CLOCK_IDLE_HIGH = 1,
};
/** First byte command mode select in slave mode */
slv_cmd_mod : bit_t;
};
/** FIFO direction setting bit */
fifo_dir : enum(1) {
[[ c: unqualified ]]
FIFO_DIR_INPUT = 1,
[[ c: unqualified ]]
FIFO_DIR_OUTPUT = 0,
};
struct {
/** SCK output enable bit */
sck_oe : enable_t;
/** MOSI output enable bit */
mosi_oe : enable_t;
/** MISO output enable bit */
miso_oe : enable_t;
} pin_enable;
};
/** SPI0 Control Configuration Register */
reg ctrl_cfg(8) : struct {
/** DMA function enable bit */
dma_enable : bit_t;
reserved(1);
/** DMA address loop enable bit */
dma_loop : bit_t;
reserved(1);
/** Auto-clear RB_SPI_IF_BYTE_END when accessing BUFFER/FIFO */
auto_if : bit_t;
/** SPI data bit sequence selection */
bit_order : bit_t;
/** Input delay enable in master mode */
mst_dly_en : bit_t;
reserved(1);
};
/** SPI0 Interrupt Enable Register */
reg inter_en(8) : struct {
/** All byte transmission completion interrupt enable bit */
ie_cnt_end : bit_t;
/** Single byte transmission completion interrupt enable bit */
ie_byte_end : bit_t;
/** More than half FIFO used interrupt enable bit */
ie_fifo_hf : bit_t;
/** DMA end interrupt enable bit */
ie_dma_end : bit_t;
/** FIFO overflow interrupt enable bit */
ie_fifo_ov : bit_t;
reserved(2);
/** Enable receiving the first byte interrupt in slave mode */
ie_fst_byte : bit_t;
};
assert_pos(0x03);
union {
/** SPI0 Clock Divider Register */
reg clock_div(8);
/** SPI0 Preset data register in slave mode. */
reg slave_pre(8);
};
assert_pos(0x04);
/** SPI0 Data Buffer Register */
reg data_buf(8);
assert_pos(0x05);
/** SPI0 Status Register */
reg status(8) : struct {
reserved(4);
/** Command receive completion in slave mode */
slv_cmd_act : bit_t;
/** FIFO ready status */
fifo_ready : bit_t;
/** First loading status after chip select in slave mode */
slv_cs_load : bit_t;
/** Chip select status in slave mode */
slv_select : bit_t;
};
assert_pos(0x06);
/** SPI0 Interrupt Flag Register */
reg int_flag(8) : struct {
/** All byte transmission completion flag */
if_cnt_end : bit_t;
/** Single byte transmission completion flag */
if_byte_end : bit_t;
/** More than half FIFO used flag */
if_fifo_hf : bit_t;
/** DMA completion flag */
if_dma_end : bit_t;
/** FIFO overflow flag */
if_fifo_ov : bit_t;
reserved(1);
/** SPI idle status */
free : bit_t;
/** First byte received flag in slave mode */
if_fst_byte : bit_t;
};
assert_pos(0x07);
/** SPI0 FIFO Count Register */
reg fifo_count(8);
skip_to(0x0C);
/** SPI0 Total Transmission Length Register */
reg total_count(16);
skip_to(0x10);
reg fifo(8);
reserved(16);
assert_pos(0x13);
reg fifo_count_1(8);
assert_pos(0x14);
/** SPI0 DMA Buffer Current Address */
reg dma_now(16);
reserved(16);
assert_pos(0x18);
/** SPI0 DMA Buffer Start Address */
reg dma_beg(16);
reserved(16);
assert_pos(0x1C);
/** SPI0 DMA Buffer End Address */
reg dma_end(16);
};
instance spi0 at spi_base : spi_t;
};
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