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author | Josh Rahm <joshuarahm@gmail.com> | 2020-11-22 01:06:30 -0700 |
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committer | Josh Rahm <joshuarahm@gmail.com> | 2020-11-22 01:06:30 -0700 |
commit | 9f28e53c71d28d04e2775c59944d2887a99f1e86 (patch) | |
tree | c0ecb2872c6d27acf08aa73919d709f949200de5 /02-usart/include/arch/stm32l4xxx/peripherals/nvic.h | |
parent | ebb9123c00d1e9629376b6f0a2f1f4e7e550c2af (diff) | |
download | stm32l4-9f28e53c71d28d04e2775c59944d2887a99f1e86.tar.gz stm32l4-9f28e53c71d28d04e2775c59944d2887a99f1e86.tar.bz2 stm32l4-9f28e53c71d28d04e2775c59944d2887a99f1e86.zip |
Large reorganization.
What was in core/ is now moved to arch/stm34l4xxx/peripherals. This new
directory is *supposed to* to contain raw header files defining just the
pertinent register structures for the various peripherals. Peripheral
management belongs somewhere in the new `kern/..` directories. This is
not completely the case at the moment, so more refactoring needs to be
done.
What was sitting in the root has now been moved into the kern/
directory. The kern/ directory is to contain everything else
other than raw device register definitions. The root of the kern/
tree is reserved for standard library-esque headers.
The kern/<peripheral> directory contains management systems for that
peripheral. (At the moment DMA is the only peripheral with a decent
management system.) Preferably these peripheral systems should only
include their correlating header in arch/stm34l4xxx/peripherals, and
use other management systems for handling other peripherals rather
than manipulating their raw registers directly. (Though this ideal
will require much more critical mass of management systems.)
Diffstat (limited to '02-usart/include/arch/stm32l4xxx/peripherals/nvic.h')
-rw-r--r-- | 02-usart/include/arch/stm32l4xxx/peripherals/nvic.h | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/02-usart/include/arch/stm32l4xxx/peripherals/nvic.h b/02-usart/include/arch/stm32l4xxx/peripherals/nvic.h new file mode 100644 index 0000000..1645a2d --- /dev/null +++ b/02-usart/include/arch/stm32l4xxx/peripherals/nvic.h @@ -0,0 +1,46 @@ +#ifndef NVIC_H_ +#define NVIC_H_ + +#include "arch.h" +#include "kern/common.h" + +typedef __IO struct { +#define nvic_intlinesnum (0x0F << 0) + uint32_t ict_r; /* Interrupt control type register. */ + + uint8_t reserved0[0xF8]; + + uint32_t ise_r[8]; + + uint8_t reserved1[0x60]; + + uint32_t ice_r[8]; + + uint8_t reserved2[0x60]; + + uint32_t isp_r[8]; + + uint8_t reserved3[0x60]; + + uint32_t icp_r[8]; + + uint8_t reserved4[0x60]; + + uint32_t iab_r[8]; + + uint8_t reserved5[0xE0]; + + uint32_t ip_r[60]; +} nvic_t; + +static_assert(offsetof(nvic_t, ise_r) == 0x00FC, "Offset check failed"); +static_assert(offsetof(nvic_t, ice_r) == 0x017C, "Offset check failed"); +static_assert(offsetof(nvic_t, isp_r) == 0x01FC, "Offset check failed"); +static_assert(offsetof(nvic_t, icp_r) == 0x027C, "Offset check failed"); +static_assert(offsetof(nvic_t, iab_r) == 0x02FC, "Offset check failed"); +static_assert(offsetof(nvic_t, ip_r) == 0x03FC, "Offset check failed"); + +#define NVIC (* (nvic_t*) NVIC_BASE) + + +#endif /* NVIC_H_ */ |