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| author | Josh Rahm <joshuarahm@gmail.com> | 2020-11-21 23:09:31 -0700 |
|---|---|---|
| committer | Josh Rahm <joshuarahm@gmail.com> | 2020-11-21 23:09:31 -0700 |
| commit | a922e19f41e25a4b9c77e95c6b5d736609dfb9f5 (patch) | |
| tree | bf7e537a001b5ac91d94ab2c0ea870efd3551d99 /02-usart/include/arch/x86_64/arch.h | |
| parent | 822c68c74ebc3ac3694f87d516f1e91f2ce1d0fe (diff) | |
| download | stm32l4-a922e19f41e25a4b9c77e95c6b5d736609dfb9f5.tar.gz stm32l4-a922e19f41e25a4b9c77e95c6b5d736609dfb9f5.tar.bz2 stm32l4-a922e19f41e25a4b9c77e95c6b5d736609dfb9f5.zip | |
Add the spi headers that define the SPI structure.
Diffstat (limited to '02-usart/include/arch/x86_64/arch.h')
| -rw-r--r-- | 02-usart/include/arch/x86_64/arch.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/02-usart/include/arch/x86_64/arch.h b/02-usart/include/arch/x86_64/arch.h index e87559b..5e1217c 100644 --- a/02-usart/include/arch/x86_64/arch.h +++ b/02-usart/include/arch/x86_64/arch.h @@ -24,6 +24,9 @@ #define SYSTEM_CONFIG_BLOCK_BASE (load_fake_scb__()) #define NVIC_BASE (load_fake_nvic__()) +#define SPI1_BASE (load_fake_spi1__()) +#define SPI3_BASE (load_fake_spi3__()) + // Pretend there's a data segement at the start of SRAM1 for more accurate // testing. #define GHOST_DATA_SEGMENT_SIZE 1234 |