Implemented DMA abstraction in the peri/dma.c source file.

This abstraction makes it much more intuitive to use the
DMA features on the STM32L4 boards.

4 files changed, 17 insertions, 18 deletions

diff --git a/02-usart/include/core/dma.h b/02-usart/include/core/dma.h
index 73bca76..8e4896d 100644
--- a/02-usart/include/core/dma.h
+++ b/02-usart/include/core/dma.h
@@ -28,7 +28,7 @@ typedef enum {
   DMA_PRIORITY_LEVEL_MEDIUM = 1,
   DMA_PRIORITY_LEVEL_HIGH = 2,
   DMA_PRIORITY_LEVEL_VERY_HIGH = 3
-} dma_priority_level;
+} dma_priority_level_t;
 
 typedef enum {
   READ_FROM_PERIPHERAL = 0,
@@ -48,7 +48,7 @@ typedef struct {
 #define dma_cc_psize    (3 <<  8) // Peripheral size
 #define dma_cc_msize    (3 << 10) // Memory size
 #define dma_cc_pl       (3 << 12) // Priority level
-#define dma_cc_mem2mem  (1 << 13) // Memory to memory mode
+#define dma_cc_mem2mem  (1 << 14) // Memory to memory mode
 
   __IO uint32_t cc_r;
 
@@ -134,13 +134,13 @@ typedef struct {
   __IO uint32_t reserved[5];
 
   /* DMA channel selection register. */
-#define c1s (0xF <<  0) // DMA channel 1 selection.
-#define c2s (0xF <<  4) // DMA channel 2 selection.
-#define c3s (0xF <<  8) // DMA channel 3 selection.
-#define c4s (0xF << 12) // DMA channel 4 selection.
-#define c5s (0xF << 16) // DMA channel 5 selection.
-#define c6s (0xF << 20) // DMA channel 6 selection.
-#define c7s (0xF << 24) // DMA channel 7 selection.
+#define dma_c1s (0xF <<  0) // DMA channel 1 selection.
+#define dma_c2s (0xF <<  4) // DMA channel 2 selection.
+#define dma_c3s (0xF <<  8) // DMA channel 3 selection.
+#define dma_c4s (0xF << 12) // DMA channel 4 selection.
+#define dma_c5s (0xF << 16) // DMA channel 5 selection.
+#define dma_c6s (0xF << 20) // DMA channel 6 selection.
+#define dma_c7s (0xF << 24) // DMA channel 7 selection.
   __IO uint32_t csel_r;
 } dma_t;
 
diff --git a/02-usart/include/core/isrs.inc b/02-usart/include/core/isrs.inc
index e45e216..0682238 100644
--- a/02-usart/include/core/isrs.inc
+++ b/02-usart/include/core/isrs.inc
@@ -75,11 +75,11 @@ IRQ(on_uart4, UART4, 68)
 IRQ(on_uart5, UART5, 69)
 IRQ(on_tim6_dacunder, TIM6_DACUNDER, 70)
 IRQ(on_tim7, TIM7, 71)
-IRQ(on_dma2_channel1, DMA2_CHANNEL1, 72)
-IRQ(on_dma2_channel2, DMA2_CHANNEL2, 73)
-IRQ(on_dma2_channel3, DMA2_CHANNEL3, 74)
-IRQ(on_dma2_channel4, DMA2_CHANNEL4, 75)
-IRQ(on_dma2_channel5, DMA2_CHANNEL5, 76)
+IRQ(on_dma2_channel1, DMA2_CHANNEL1_IRQ, 72)
+IRQ(on_dma2_channel2, DMA2_CHANNEL2_IRQ, 73)
+IRQ(on_dma2_channel3, DMA2_CHANNEL3_IRQ, 74)
+IRQ(on_dma2_channel4, DMA2_CHANNEL4_IRQ, 75)
+IRQ(on_dma2_channel5, DMA2_CHANNEL5_IRQ, 76)
 IRQ(on_dfsdm1_flt0, DFSDM1_FLT0, 77)
 IRQ(on_dfsdm1_flt1, DFSDM1_FLT1, 78)
 IRQ(on_dfsdm1_flt2, DFSDM1_FLT2, 79)
diff --git a/02-usart/include/core/rcc.h b/02-usart/include/core/rcc.h
index 9c82501..45f64b5 100644
--- a/02-usart/include/core/rcc.h
+++ b/02-usart/include/core/rcc.h
@@ -1,11 +1,10 @@
 #ifndef H__RCC_
 #define H__RCC_
 
+#include "arch.h"
 #include "common.h"
 #include <stdint.h>
 
-#define RCC_BASE ((uint32_t)0x40021000)
-
 typedef struct {
   __IO uint32_t c_r;      /* Clock control register. 0x00 */
   __IO uint32_t icsc_r;   /* Internal clock srcs calibration register. 0x04 */
diff --git a/02-usart/include/core/usart.h b/02-usart/include/core/usart.h
index 667b931..8d841df 100644
--- a/02-usart/include/core/usart.h
+++ b/02-usart/include/core/usart.h
@@ -8,8 +8,8 @@
 #include "rcc.h"
 #include <assert.h>
 
-#define USART1 (* (__IO usart_t*) USART1_BASE)
-#define USART2 (* (__IO usart_t*) USART2_BASE)
+#define USART1 (* (usart_t*) USART1_BASE)
+#define USART2 (* (usart_t*) USART2_BASE)
 
 /*
  * Possible USART clock sources.