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author | Josh Rahm <joshuarahm@gmail.com> | 2020-11-18 21:11:01 -0700 |
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committer | Josh Rahm <joshuarahm@gmail.com> | 2020-11-18 21:16:12 -0700 |
commit | c1405b06d98b9b227fa7ff53c158f31d745eb505 (patch) | |
tree | 77397453c2b0e20bbb4136aa52836fe3eb0e41e6 /02-usart/src/core/isr_vector.c | |
parent | 44c2d2d5e5ce43563a4912b2967cdb6b2039b6dd (diff) | |
download | stm32l4-c1405b06d98b9b227fa7ff53c158f31d745eb505.tar.gz stm32l4-c1405b06d98b9b227fa7ff53c158f31d745eb505.tar.bz2 stm32l4-c1405b06d98b9b227fa7ff53c158f31d745eb505.zip |
Reorganize some file. Put thte core register libraries in a core/
subdirectory.
Diffstat (limited to '02-usart/src/core/isr_vector.c')
-rw-r--r-- | 02-usart/src/core/isr_vector.c | 107 |
1 files changed, 107 insertions, 0 deletions
diff --git a/02-usart/src/core/isr_vector.c b/02-usart/src/core/isr_vector.c new file mode 100644 index 0000000..9f3f560 --- /dev/null +++ b/02-usart/src/core/isr_vector.c @@ -0,0 +1,107 @@ +#include "core/isr_vector.h" +#include "core/gpio.h" + +#include "arch.h" +#include "delay.h" + +#ifdef ARCH_STM32L4 + +#define IRQ_RESERVED(n) +#define IRQ(name, n) \ + void WEAK name () { \ + unhandled_isr(n); \ + } +#include "core/isrs.i" +#undef IRQ_RESERVED +#undef IRQ + + +void isr_simple_pin_on() +{ + __IO gpio_port_t* port_b = enable_gpio(GPIO_PORT_B); + gpio_output_pin_t pin3 = set_gpio_pin_output(port_b, PIN_3); + + pin_on(pin3); +} + +#define DEFINE_UNHANDLED_ISR(n) \ + int unhandled_isr_##n() \ + { \ + unhandled_isr(n); \ + } + + +/* Flashes wildly. */ +void super_flash() +{ + static int pin_on = 0; + __IO gpio_port_t* port_b = enable_gpio(GPIO_PORT_B); + gpio_output_pin_t pin3 = set_gpio_pin_output(port_b, PIN_3); + + if (pin_on) { + pin_off(pin3); + } else { + pin_on(pin3); + } + + pin_on = !pin_on; +} + +#define IRQ_RESERVED(n) 0, +#define IRQ(name, n) name, +const void* vectors[] __attribute__((section(".vectors"))) = { + (void*)0x2000c000, /* Top of stack at top of sram1. 48k */ +#include "core/isrs.i" +}; +#undef IRQ_RESERVED +#undef IRQ + +/* Encodes the provided number as a series of flashes on the on-board + * LED. The flashes follow as such: + * + * Before the bits of the code are flashed, a rapid succession of 20 flashes + * followed by a pause will occur indicating that the next 8 flashes indicate + * the bits of the provided code. + * + * The next eight flashes are indicate either a 1 or 0 depending on the length + * of the light being on. The first flash is the least-significant bit, the next + * the second least, the third third least, etc. + * + * - A quick flash followed by a long pause indicates a 0 bit. + * - A "long" flash followed by a equally long pause indicates a 1 bit. + */ +void unhandled_isr(uint8_t number) +{ + __IO gpio_port_t* port_b = enable_gpio(GPIO_PORT_B); + gpio_output_pin_t pin3 = set_gpio_pin_output(port_b, PIN_3); + for (;;) { + for (int i = 0; i < 20; ++ i) { + pin_on(pin3); + delay(1000000); + pin_off(pin3); + delay(1000000); + } + delay(50000000); + + int n = number; + for (int i = 0; i < 8; ++ i) { + if (n & 1) { + // LSB is a 1 + pin_on(pin3); + delay(15000000); + pin_off(pin3); + delay(15000000); + } else { + // LSB is a 0 + pin_on(pin3); + delay(1000000); + pin_off(pin3); + delay(29000000); + } + + n >>= 1; + } + } +} + +#endif |