diff options
author | Josh Rahm <joshuarahm@gmail.com> | 2018-01-23 23:14:31 -0700 |
---|---|---|
committer | Josh Rahm <joshuarahm@gmail.com> | 2018-01-23 23:14:31 -0700 |
commit | 7aa10db46c13ad8adc88aadff39b8cf6b15db09d (patch) | |
tree | b1e34a6703de33250b0bd97d34999b687a36a00f /02-usart/src/usart.c | |
parent | acd8afd83da625d36ef39bc01717f29f3b689952 (diff) | |
download | stm32l4-7aa10db46c13ad8adc88aadff39b8cf6b15db09d.tar.gz stm32l4-7aa10db46c13ad8adc88aadff39b8cf6b15db09d.tar.bz2 stm32l4-7aa10db46c13ad8adc88aadff39b8cf6b15db09d.zip |
rename folders to give notion of progression
Diffstat (limited to '02-usart/src/usart.c')
-rw-r--r-- | 02-usart/src/usart.c | 80 |
1 files changed, 80 insertions, 0 deletions
diff --git a/02-usart/src/usart.c b/02-usart/src/usart.c new file mode 100644 index 0000000..eddfbe7 --- /dev/null +++ b/02-usart/src/usart.c @@ -0,0 +1,80 @@ +#include "usart.h" +#include "delay.h" + +void set_usart1_clock_src(__IO rcc_t* rcc, usart_clk_src_t usart_clk_src) +{ + rcc->ccip_r = rcc->ccip_r & (~0x03) | usart_clk_src; +} + +void set_usart2_clock_src(__IO rcc_t* rcc, usart_clk_src_t usart_clk_src) +{ + rcc->ccip_r = rcc->ccip_r & ~(0x03 << 2) | (usart_clk_src << 2); +} + +void set_usart2_clock_enabled(__IO rcc_t* rcc, bool enable) +{ + if (enable) { + rcc->apb1en1_r |= BIT(17); + } else { + rcc->apb1en1_r &= ~BIT(17); + } +} + +void set_usart1_clock_enabled(__IO rcc_t* rcc, bool enable) +{ + if (enable) { + rcc->apb2en_r |= BIT(14); + } else { + rcc->apb2en_r &= ~BIT(14); + } +} + +void usart_set_parity(__IO usart_t* usart, usart_parity_t parity) +{ + uint32_t c_r1 = usart->c_r1; + c_r1 &= ~(0x3 << 9); + c_r1 |= parity; + usart->c_r1 = c_r1; +} + +void usart_set_enabled(__IO usart_t* usart, usart_enable_t enabled) +{ + uint32_t c_r1 = usart->c_r1; + + if (!enabled) { + usart->c1_bf.ue = 0; + } else { + /* Set the rx enabled. */ + usart->c1_bf.re = !!(enabled & USART_ENABLE_RX); + usart->c1_bf.te = !!(enabled & USART_ENABLE_TX); + usart->c1_bf.ue = 1; + } +} + +void usart_transmit_byte(__IO usart_t* usart, uint8_t byte) +{ + usart->td_r = byte; + /* Per the manual, when bit 7 of the IS register is set, then the usart + * data has been sent to the shift register. + * + * This bit is cleared by writing to the TD register. */ + while (!(usart->is_r & BIT(7))) + ; +} + +void usart_transmit_bytes(__IO usart_t* usart, const uint8_t* bytes, uint32_t n) +{ + while (n --) { + usart_transmit_byte(usart, *(bytes ++)); + } +} + +void usart_transmit_str(__IO usart_t* usart, const char* str) +{ + while (*str) { + if (*str == '\n') { + usart_transmit_byte(usart, '\r'); + } + usart_transmit_byte(usart, *(str ++)); + } +} |