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author | Josh Rahm <joshuarahm@gmail.com> | 2018-01-24 00:12:03 -0700 |
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committer | Josh Rahm <joshuarahm@gmail.com> | 2018-01-24 00:12:03 -0700 |
commit | 80360c4b8361320b726897c86ee13f9b4caf004a (patch) | |
tree | 9a590055e440025d7d36701a540d9e7e39c082d4 /03-refactor/include/usart.h | |
parent | 2545ae2d57e5b70975e3fd3b3e570da13dbf62f0 (diff) | |
download | stm32l4-80360c4b8361320b726897c86ee13f9b4caf004a.tar.gz stm32l4-80360c4b8361320b726897c86ee13f9b4caf004a.tar.bz2 stm32l4-80360c4b8361320b726897c86ee13f9b4caf004a.zip |
More fields in USART and RCC set to use bitfields.
Diffstat (limited to '03-refactor/include/usart.h')
-rw-r--r-- | 03-refactor/include/usart.h | 126 |
1 files changed, 103 insertions, 23 deletions
diff --git a/03-refactor/include/usart.h b/03-refactor/include/usart.h index 257aab6..3fea253 100644 --- a/03-refactor/include/usart.h +++ b/03-refactor/include/usart.h @@ -17,9 +17,9 @@ typedef enum { } usart_clk_src_t; typedef struct { - /* USART configuration registers 0x04 - 0x0c. */ - union { - uint32_t c_r1; + /* USART conttrol register 1. */ + union USART_CR1 { + __IO uint32_t r; struct { bits_t ue:1; /* UART enable */ bits_t uesm:1; /* UART enabled in stop mode. */ @@ -29,6 +29,7 @@ typedef struct { bits_t rxneie:1; /* RXNEIE RXNE interrupt enable. */ bits_t tcie:1; bits_t txeie:1; + bits_t peie:1; bits_t ps:1; bits_t pce:1; @@ -37,19 +38,103 @@ typedef struct { bits_t mme:1; bits_t cmie:1; bits_t over8:1; - bits_t dedt:4; - bits_t deat:4; + + bits_t dedt:5; + bits_t deat:5; + bits_t rtoie:1; bits_t eobie:1; bits_t m1:1; bits_t reserved:3; - } PACKED c1_bf; - }; - uint32_t c_r2; - uint32_t c_r3; + } PACKED; + } __IO c1; + + /* USART control register 2. */ + union USART_CR2 { + __IO uint32_t r; + + struct { + RESERVED(4); + bits_t addm7:1; + bits_t lbdl:1; + bits_t lbdie:1; + RESERVED(1); + + bits_t lbcl:1; + bits_t cpha:1; + bits_t cpol:1; + bits_t clken:1; + bits_t stop:2; + bits_t linen:1; + bits_t swap:1; + + bits_t rxinv:1; + bits_t txinv:1; + bits_t datainv:1; + bits_t msbfirst:1; + bits_t abren:1; + bits_t abrmod:2; + bits_t rtoen:1; + + bits_t add:8; + } PACKED; + } __IO c2; + + union USART_CR3 { + __IO uint32_t r; + + struct { + bits_t eie:1; + bits_t iren:1; + bits_t irlp:1; + bits_t hdsel:1; + bits_t nack:1; + bits_t scen:1; + bits_t dmar:1; + bits_t dmat:1; + + bits_t rtse:1; + bits_t ctse:1; + bits_t ctsie:1; + bits_t onebit:1; + bits_t ovrdis:1; + bits_t ddre:1; + bits_t dem:1; + bits_t dep:1; + + RESERVED(1); + bits_t scarcnt:3; + bits_t wus:2; + bits_t wufie:1; + bits_t ucesm:1; + + bits_t tcbgtie:1; + RESERVED(7); + } PACKED; + } __IO c3; /* USART baud rate register. */ - uint32_t br_r; + union USART_BRR { + __IO uint32_t r; + + struct { + uint16_t v; + RESERVED(16); + } PACKED; + + /* Structure to use when OVER8 is set in the control register + * USART_C1. */ + struct { + bits_t low:3; + + RESERVED(1); + + bits_t high:12; + + RESERVED(16); + } PACKED over8; + } __IO br; + uint32_t gtp_r; uint32_t rto_r; uint32_t rq_r; @@ -68,16 +153,15 @@ typedef enum { static inline void usart_set_divisor( __IO usart_t* usart, - uint32_t usartdiv) + uint16_t usartdiv) { - if (usart->c_r1 & (1 << 15)) { + if (usart->c1.r & (1 << 15)) { /* OVER8 is set. */ - usart->br_r = - (usartdiv & ~7) | - ((usartdiv & 7) >> 1); + usart->br.over8.high = (usartdiv & ~7); + usart->br.over8.low = ((usartdiv & 7) >> 1); } else { /* OVER8 is not set. */ - usart->br_r = usartdiv; + usart->br.v = usartdiv; } } @@ -85,17 +169,13 @@ static inline void usart_set_oversampling_mode( __IO usart_t* usart, oversampling_mode_t mode) { - if (mode == OVERSAMPLE_8) { - usart->c_r1 |= 1 << 15; - } else { - usart->c_r1 &= ~(1 << 15); - } + usart->c1.over8 = mode == OVERSAMPLE_8; } typedef enum { USART_PARITY_DISABLED = 0, - USART_PARITY_EVEN = 2 << 9, - USART_PARITY_ODD = 3 << 9, + USART_PARITY_ODD = 1, + USART_PARITY_EVEN = 2, } usart_parity_t; typedef enum { |