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authorJosh Rahm <joshuarahm@gmail.com>2018-01-24 00:19:51 -0700
committerJosh Rahm <joshuarahm@gmail.com>2018-01-24 00:20:01 -0700
commit109cdf120ea85f46d664e77c44ea2a311fd49ba2 (patch)
tree67350219afd13ce0b02111b6af2aa936bb7c9ebb
parent80360c4b8361320b726897c86ee13f9b4caf004a (diff)
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Small changes in styling to separate bits by octets.
-rw-r--r--03-refactor/include/rcc.h4
-rw-r--r--03-refactor/src/usart.c10
2 files changed, 8 insertions, 6 deletions
diff --git a/03-refactor/include/rcc.h b/03-refactor/include/rcc.h
index 827d66f..3c55e67 100644
--- a/03-refactor/include/rcc.h
+++ b/03-refactor/include/rcc.h
@@ -32,25 +32,23 @@ typedef struct {
bits_t msipllen:1; /* Enabled/disable the PLL part of MSI. */
bits_t msirgsel:1; /* MSI clock range selection. */
bits_t msirange:4; /* MSI range. */
+
bits_t hsion:1; /* Enable the HSI16 clock. */
bits_t hsikeron:1; /* Force the HSI16 ON even in stop modes. */
bits_t hsirdy:1; /* Is the hsi ready? */
bits_t hsiasfs:1; /* HSI automatic start from STOP. */
-
RESERVED(4);
bits_t hseon:1; /* Enable the HSE. */
bits_t hserdy:1; /* Is the HSE ready? */
bits_t hsebyp:1; /* Use an external HSE. */
bits_t csson:1; /* Clock security system enabled. */
-
RESERVED(4);
bits_t pllon:1; /* Enable the main PLL. */
bits_t pllrdy:1; /* Is the PLL ready? */
bits_t pllsai1on:1; /* Enable the SAI1 PLL. */
bits_t pllsai1rdy:1; /* Enable the SAI1 PLL. */
-
RESERVED(4);
} PACKED;
} __IO c;
diff --git a/03-refactor/src/usart.c b/03-refactor/src/usart.c
index a3b0061..fc58467 100644
--- a/03-refactor/src/usart.c
+++ b/03-refactor/src/usart.c
@@ -41,9 +41,13 @@ void usart_set_enabled(__IO usart_t* usart, usart_enable_t enabled)
usart->c1.ue = 0;
} else {
/* Set the rx enabled. */
- usart->c1.re = !!(enabled & USART_ENABLE_RX);
- usart->c1.te = !!(enabled & USART_ENABLE_TX);
- usart->c1.ue = 1;
+ union USART_CR1 tmp = usart->c1;
+
+ tmp.re = !!(enabled & USART_ENABLE_RX);
+ tmp.te = !!(enabled & USART_ENABLE_TX);
+ tmp.ue = 1;
+
+ usart->c1 = tmp;
}
}