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authorJosh Rahm <joshuarahm@gmail.com>2020-11-24 13:46:41 -0700
committerJosh Rahm <joshuarahm@gmail.com>2020-11-24 13:46:41 -0700
commit93b063fedfcf7409a67df035170ea5670cad22e1 (patch)
treea23321a7465d966b1ccf196ca00e65a70c9f9110 /include/arch/x86_64
parentb040195d31df6ad759f16ea3456471897f55daa1 (diff)
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Moved action to top level.
Removed old iterations of the project and moved the files from 02-usart to the root directory since that's the sole place where the action is and that subproject has outgrown its initial title.
Diffstat (limited to 'include/arch/x86_64')
-rw-r--r--include/arch/x86_64/arch.h37
1 files changed, 37 insertions, 0 deletions
diff --git a/include/arch/x86_64/arch.h b/include/arch/x86_64/arch.h
new file mode 100644
index 0000000..c17721d
--- /dev/null
+++ b/include/arch/x86_64/arch.h
@@ -0,0 +1,37 @@
+#ifndef ARCH_H_
+#define ARCH_H_
+
+#include "fake_env.h"
+
+#define ARCH_PC
+#define enable_all_interrupts() do {} while(0)
+
+#define RCC_BASE (load_fake_rcc__())
+
+#define DMA1_BASE (load_fake_ahb1__() + 0x0)
+#define DMA2_BASE (load_fake_ahb1__() + 0x400)
+
+#define USART1_BASE (load_fake_apb2__() + 0x3800)
+#define USART2_BASE (load_fake_apb1__() + 0x4400)
+
+#define GPIOA_BASE (load_fake_ahb2__() + 0x0)
+#define GPIOB_BASE (load_fake_ahb2__() + 0x400)
+#define GPIOC_BASE (load_fake_ahb2__() + 0x800)
+#define GPIOH_BASE (load_fake_ahb2__() + 0x1C00)
+
+#define SRAM1_BASE (load_fake_sram1__() + 0x0)
+#define SRAM2_BASE (load_fake_sram2__() + 0x0)
+
+#define SYSTEM_CONFIG_BLOCK_BASE (load_fake_scb__())
+#define NVIC_BASE (load_fake_nvic__())
+
+#define SPI1_BASE (load_fake_spi1__())
+#define SPI3_BASE (load_fake_spi3__())
+
+// Pretend there's a data segement at the start of SRAM1 for more accurate
+// testing.
+#define GHOST_DATA_SEGMENT_SIZE 1234
+#define DATA_SEGMENT_START (*((uint8_t*)SRAM1_BASE))
+#define DATA_SEGMENT_STOP (*(((uint8_t*)SRAM1_BASE) + GHOST_DATA_SEGMENT_SIZE))
+
+#endif /* ARCH_H_ */