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authorJosh Rahm <joshuarahm@gmail.com>2020-11-24 14:03:19 -0700
committerJosh Rahm <joshuarahm@gmail.com>2020-11-24 14:03:19 -0700
commit351ff7059a5bacb322664412a8c62ee4640b33bf (patch)
tree53ef3fb16c5742c2edc45e633d80f6e16896f864 /src/kern/dma
parent6a1e0acc14b62c00317ac61c6ad6d8ffe441be4f (diff)
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Update .clang-format and run it on filse
Diffstat (limited to 'src/kern/dma')
-rw-r--r--src/kern/dma/dma_manager.c84
1 files changed, 35 insertions, 49 deletions
diff --git a/src/kern/dma/dma_manager.c b/src/kern/dma/dma_manager.c
index 00e9f3d..9ffa795 100644
--- a/src/kern/dma/dma_manager.c
+++ b/src/kern/dma/dma_manager.c
@@ -1,8 +1,8 @@
#include "kern/dma/dma_manager.h"
+
#include "arch/stm32l4xxx/peripherals/dma.h"
-#include "arch/stm32l4xxx/peripherals/usart.h"
#include "arch/stm32l4xxx/peripherals/rcc.h"
-
+#include "arch/stm32l4xxx/peripherals/usart.h"
/* Bitmask of DMA2 channels in use. */
static uint8_t dma_inuse[2];
@@ -29,7 +29,9 @@ static dma_channel_config_t* get_raw_channel_config(dma_channel_t chan)
static uint32_t get_periph_location(dma_peripheral_t operipheral)
{
-#define CASE(p, n) case p: return ptr2reg(n);
+#define CASE(p, n) \
+ case p: \
+ return ptr2reg(n);
switch (operipheral) {
CASE(DMA1_PERIPH_USART1_RX, &USART1.rd_r)
CASE(DMA1_PERIPH_USART1_TX, &USART1.td_r)
@@ -53,10 +55,7 @@ static dma_channel_t allocate_dma_channel(
int chan = peripheral % DMA_N_CHANNELS;
*modesel = peripheral / 7;
- return (dma_channel_t) {
- .dma = dmasel,
- .chan = chan
- };
+ return (dma_channel_t){.dma = dmasel, .chan = chan};
}
/*
@@ -66,11 +65,9 @@ static dma_channel_t allocate_dma_channel(
* Returns 0 if this function was unable to reserve
* the channel.
*/
-static int try_reserve_dma_channel(
- dma_channel_t chan)
+static int try_reserve_dma_channel(dma_channel_t chan)
{
- int in_use = __sync_fetch_and_or(
- &dma_inuse[chan.dma], 1 << chan.chan);
+ int in_use = __sync_fetch_and_or(&dma_inuse[chan.dma], 1 << chan.chan);
return !(in_use & (1 << chan.chan));
}
@@ -108,21 +105,20 @@ void configure_dma_channel(
dma_t* dma = get_raw_dma(chan);
regset(dma->csel_r, 0xF << (4 * chan.chan), selmode);
- dma_channel_config_t* config =
- &dma->channel_config[chan.chan];
+ dma_channel_config_t* config = &dma->channel_config[chan.chan];
uint32_t reg = 0;
- regset(reg, dma_cc_dir, dir);
- regset(reg, dma_cc_tcie, opts->transfer_complete_interrupt_enable);
- regset(reg, dma_cc_htie, opts->half_transfer_interrupt_enable);
- regset(reg, dma_cc_teie, opts->transfer_error_interrupt_enable);
- regset(reg, dma_cc_circ, opts->circular_mode);
- regset(reg, dma_cc_pinc, opts->peripheral_increment);
- regset(reg, dma_cc_minc, opts->memory_increment);
- regset(reg, dma_cc_psize, opts->peripheral_block_size);
- regset(reg, dma_cc_msize, opts->memory_block_size);
- regset(reg, dma_cc_pl, opts->priority);
+ regset(reg, dma_cc_dir, dir);
+ regset(reg, dma_cc_tcie, opts->transfer_complete_interrupt_enable);
+ regset(reg, dma_cc_htie, opts->half_transfer_interrupt_enable);
+ regset(reg, dma_cc_teie, opts->transfer_error_interrupt_enable);
+ regset(reg, dma_cc_circ, opts->circular_mode);
+ regset(reg, dma_cc_pinc, opts->peripheral_increment);
+ regset(reg, dma_cc_minc, opts->memory_increment);
+ regset(reg, dma_cc_psize, opts->peripheral_block_size);
+ regset(reg, dma_cc_msize, opts->memory_block_size);
+ regset(reg, dma_cc_pl, opts->priority);
regset(reg, dma_cc_mem2mem, mem2mem);
config->cc_r = reg;
@@ -132,12 +128,9 @@ void configure_dma_channel(
}
dma_mem2mem_channel_t select_dma_channel_mem2mem(
- int channel,
- dma_opts_t* opts,
- int* error_out)
+ int channel, dma_opts_t* opts, int* error_out)
{
-
-#define WRAP(c) ((dma_mem2mem_channel_t) { .c_ = c })
+#define WRAP(c) ((dma_mem2mem_channel_t){.c_ = c})
// TODO this should probably be in a critical section.
dma_channel_t chan;
if (channel == -1) {
@@ -189,16 +182,13 @@ dma_mem2mem_channel_t select_dma_channel_mem2mem(
}
dma_mem2p_channel_t select_dma_channel_mem2p(
- dma_peripheral_t peripheral,
- dma_opts_t* opts_in,
- int* error_out)
+ dma_peripheral_t peripheral, dma_opts_t* opts_in, int* error_out)
{
-#define WRAP(c) ((dma_mem2p_channel_t) { .c_ = c })
+#define WRAP(c) ((dma_mem2p_channel_t){.c_ = c})
*error_out = 0;
int modesel;
- dma_channel_t ret =
- allocate_dma_channel(peripheral, &modesel);
+ dma_channel_t ret = allocate_dma_channel(peripheral, &modesel);
if (!try_reserve_dma_channel(ret)) {
*error_out = DMA_ERROR_CHANNEL_IN_USE;
@@ -217,23 +207,20 @@ dma_mem2p_channel_t select_dma_channel_mem2p(
if (*error_out) {
return WRAP(DMA_CHAN_ERROR);
}
-
+
*error_out = 0;
return WRAP(ret);
#undef WRAP
}
dma_p2mem_channel_t select_dma_channel_p2mem(
- dma_peripheral_t peripheral,
- dma_opts_t* opts_in,
- int* error_out)
+ dma_peripheral_t peripheral, dma_opts_t* opts_in, int* error_out)
{
-#define WRAP(c) ((dma_p2mem_channel_t) { .c_ = c })
+#define WRAP(c) ((dma_p2mem_channel_t){.c_ = c})
*error_out = 0;
int modesel;
- dma_channel_t ret =
- allocate_dma_channel(peripheral, &modesel);
+ dma_channel_t ret = allocate_dma_channel(peripheral, &modesel);
if (!try_reserve_dma_channel(ret)) {
*error_out = DMA_ERROR_CHANNEL_IN_USE;
@@ -252,13 +239,12 @@ dma_p2mem_channel_t select_dma_channel_p2mem(
if (*error_out) {
return WRAP(DMA_CHAN_ERROR);
}
-
+
*error_out = 0;
return WRAP(ret);
#undef WRAP
}
-
void dma_mem2p_initiate_transfer(
dma_mem2p_channel_t chan, const void* from_loc, uint16_t nblocks)
{
@@ -300,12 +286,12 @@ interrupt_t dma_channel_get_interrupt(dma_channel_t chan)
return IRQ_DMA1_CHANNEL1_IRQ + chan.chan;
} else {
switch (chan.chan) {
- case 5:
- return IRQ_DMA1_CHANNEL6_IRQ;
- case 6:
- return IRQ_DMA1_CHANNEL7_IRQ;
- default:
- return IRQ_DMA2_CHANNEL1_IRQ + chan.chan;
+ case 5:
+ return IRQ_DMA1_CHANNEL6_IRQ;
+ case 6:
+ return IRQ_DMA1_CHANNEL7_IRQ;
+ default:
+ return IRQ_DMA2_CHANNEL1_IRQ + chan.chan;
}
}
}