able to set the clock speed in MHz.

5 files changed, 196 insertions, 33 deletions

diff --git a/system-clock/include/clock.h b/system-clock/include/clock.h
index 2ba6880..98574d1 100644
--- a/system-clock/include/clock.h
+++ b/system-clock/include/clock.h
@@ -2,10 +2,10 @@
 #define CLOCK_H__
 
 #include <stdint.h>
+#include "rcc.h"
 
 #define PERIPH_BASE    ((uint32_t)       0x40000000)
 #define AHBPERIPH_BASE (PERIPH_BASE +    0x00020000)
-#define RCC_BASE       (AHBPERIPH_BASE + 0x00001000)
 #define FLASH_R_BASE   (AHBPERIPH_BASE + 0x00003C00)
 #define PWR_BASE       (PERIPH_BASE + 0x7000)
 #define  PWR_CSR_VOSF                        ((uint16_t)0x0010)     /*!< Voltage Scaling select flag */
@@ -20,42 +20,102 @@ typedef struct {
   __IO uint32_t csr;
 } pwr_t;
 
-typedef struct {
-  __IO uint32_t acr;
-  __IO uint32_t pecr;
-  __IO uint32_t pdkeyr;
-  __IO uint32_t pekeyr;
-  __IO uint32_t prgkeyr;
-  __IO uint32_t optkeyr;
-  __IO uint32_t sr;
-  __IO uint32_t obr;
-  __IO uint32_t wrpr;       
-} flash_t;
+// typedef struct {
+//   __IO uint32_t acr;
+//   __IO uint32_t pecr;
+//   __IO uint32_t pdkeyr;
+//   __IO uint32_t pekeyr;
+//   __IO uint32_t prgkeyr;
+//   __IO uint32_t optkeyr;
+//   __IO uint32_t sr;
+//   __IO uint32_t obr;
+//   __IO uint32_t wrpr;       
+// } flash_t;
 
-typedef struct {
-  __IO uint32_t cr;
-  __IO uint32_t icscr;
-  __IO uint32_t cfgr;
-  __IO uint32_t cir;
-  __IO uint32_t ahbrstr;
-  __IO uint32_t apb2rstr;
-  __IO uint32_t apb1rstr;
-  __IO uint32_t ahbenr;
-  __IO uint32_t apb2enr;
-  __IO uint32_t apb1enr;
-  __IO uint32_t ahblpenr;
-  __IO uint32_t apb2lpenr;
-  __IO uint32_t apb1lpenr;      
-  __IO uint32_t csr;    
-} rcc_t;
-
-#define RCC (*(rcc_t*) (RCC_BASE))
-#define FLASH (*(flash_t*) (FLASH_R_BASE))
+// #define FLASH (*(flash_t*) (FLASH_R_BASE))
 #define PWR (*(pwr_t*) (PWR_BASE))
 
+
+/* Valid values for the PLLR/PLLQ bits of the PLLCFG register. */
+typedef enum {
+  PLL_DIVISOR_2   = 1,
+  PLL_DIVISOR_4   = 3,
+  PLL_DIVISOR_6   = 5,
+  PLL_DIVISOR_8   = 7,
+  PLL_DIVISOR_OFF = 0,
+} pll_divisor_t;
+
+/* Valid values for the PLLP bits off the PLLCFG register. */
+typedef enum  {
+  PLLP_DIVISOR_7   = 1,
+  PLLP_DIVISOR_17  = 3,
+  PLLP_DIVISOR_OFF = 0,
+} pllp_divisor_t;
+
+/* Valid values for the PLLM bits of the PLLCFG register. */
+typedef enum {
+  PLLM_DIVISOR_1 = 0,
+  PLLM_DIVISOR_2 = 1,
+  PLLM_DIVISOR_3 = 2,
+  PLLM_DIVISOR_4 = 3,
+  PLLM_DIVISOR_5 = 4,
+  PLLM_DIVISOR_6 = 5,
+  PLLM_DIVISOR_7 = 6,
+  PLLM_DIVISOR_8 = 7,
+} pllm_divisor_t;
+
+/* Possible sources for the input clock. */
+typedef enum {
+  PLL_SRC_NONE = 0,
+  PLL_SRC_MSI  = 1,
+  PLL_SRC_HSI  = 2,
+  PLL_SRC_HSE  = 3,
+} pll_src_t;
+
+/* Valid sources for the system clock. */
+typedef enum {
+  SYSTEM_CLOCK_SRC_MSI = 0,
+  SYSTEM_CLOCK_SRC_HSI = 1,
+  SYSTEM_CLOCK_SRC_HSE = 2,
+  SYSTEM_CLOCK_SRC_PLL = 3,
+} system_clock_src_t;
+
+#define E_BADPLLN (-2)
+#define E_BADPLLP_DIV (-1)
+#define E_TIMEOUT (-3)
+#define E_NOT_OFF (-4)
+#define E_BAD_ARG (-5)
+
 /*
  * Sets the system clock to a full 80Mhz.
  */
-int set_sys_clock();
+int set_system_clock_MHz(uint8_t mhz);
+
+/*
+ * Set the PLL on.
+ */
+int pll_on();
+
+/*
+ * Set the PLL off.
+ */
+int pll_off();
+
+/*
+ * Sets the source of the system clock.
+ */
+int set_system_clock_src(system_clock_src_t src);
+
+/*
+ * Configure the PLL.
+ */
+int configure_pll(
+    uint8_t pllp_div_factor,
+    pll_divisor_t  pllr,  /* System clock divisor. */
+    pll_divisor_t  pllq,  /* Divison factor for PLL48M1CLK. */
+    pllp_divisor_t pllp,  /* Divison factor for PLLSAI2CLK. */
+    uint8_t        plln,  /* PLL numerator. */
+    pllm_divisor_t pllm,  /* PLL denominator. */
+    pll_src_t      pllsrc /* PLL source */ );
 
 #endif /* CLOCK_H__ */
diff --git a/system-clock/include/common.h b/system-clock/include/common.h
index f58f179..6fc701c 100644
--- a/system-clock/include/common.h
+++ b/system-clock/include/common.h
@@ -9,5 +9,6 @@
 #define bool int
 
 #define PACKED __attribute__((packed))
+#define BIT(n) (1 << (n))
 
 #endif /* COMMON_H */
diff --git a/system-clock/include/flash.h b/system-clock/include/flash.h
new file mode 100644
index 0000000..ac63bf9
--- /dev/null
+++ b/system-clock/include/flash.h
@@ -0,0 +1,20 @@
+#ifndef H__FLASH_
+#define H__FLASH_
+
+#include "common.h"
+
+/*
+ * Header file for dealing with flash.
+ */
+
+#define FLASH_BASE      0x40022000
+
+typedef struct {
+  __IO uint32_t ac_r; /* Flash access control register. */
+
+  /* TODO fill out the rest. */
+} PACKED flash_t;
+
+#define FLASH (*(__IO flash_t*) FLASH_BASE)
+
+#endif /* H__FLASH_ */
diff --git a/system-clock/include/rcc.h b/system-clock/include/rcc.h
new file mode 100644
index 0000000..4206dc1
--- /dev/null
+++ b/system-clock/include/rcc.h
@@ -0,0 +1,82 @@
+#ifndef H__RCC_
+#define H__RCC_
+
+#include "common.h"
+
+#define RCC_BASE ((uint32_t) 0x40021000)
+
+typedef struct {
+  __IO uint32_t c_r;       /* Clock control register. 0x00 */
+  __IO uint32_t icsc_r;    /* Internal clock srcs calibration register. 0x04 */
+  __IO uint32_t cfg_r;     /* clock confguration register. 0x08 */
+  __IO uint32_t pllcfg_r;  /* PLL Configuration register. 0x0c */
+  __IO uint32_t pllsai1cfg_r;  /* PLLSAI1 configuration register. 0x10 */
+
+  __IO uint32_t reserved_1; /* Not used. offset 0x14. */
+
+  __IO uint32_t cie_r;     /* Clock interrupt enable register. 0x18 */
+  __IO uint32_t cif_r;     /* Clock interrupt flag regiseter.  0x1c */
+  __IO uint32_t cic_r;     /* Clock interrupt clear register.  0x20 */
+
+  __IO uint32_t reserved_2; /* Not used. offset 0x24. */
+
+  __IO uint32_t ahb1rst_r;  /* AHB Peripheral 1 reset register. 0x28 */
+  __IO uint32_t ahb2rst_r;  /* AHB Peripheral 2 reset register. 0x2c */
+  __IO uint32_t ahb3rst_r;  /* AHB Peripheral 3 reset register. 0x30 */
+
+  __IO uint32_t reserved_3; /* Not used. offset 0x34. */
+
+  __IO uint32_t abp1rst1_r; /* APB Peripheral reset register 1. 0x38 */
+  __IO uint32_t abp1rst2_r; /* APB Peripheral reset register 2. 0x3C */
+  __IO uint32_t abp2rst_r;  /* APB Peripheral reset register.   0x40 */
+
+  __IO uint32_t reserved_4; /* Not used. offset 0x44. */
+
+  __IO uint32_t ahb1en_r;  /* AHB1 Peripheral enable register. 0x48 */
+  __IO uint32_t ahb2en_r;  /* AHB2 Peripheral enable register. 0x4C */
+  __IO uint32_t ahb3en_r;  /* AHB3 Peripheral enable register. 0x50 */
+
+  __IO uint32_t reserved_5; /* Not used. offset 0x54. */
+
+  __IO uint32_t apb1en1_r;  /* APB1 Peripheral enable register 1. 0x58 */
+  __IO uint32_t apb1en2_r;  /* APB1 Peripheral enable register 2. 0x5C */
+  __IO uint32_t apb2en_r;   /* APB2 Peripheral enable register.   0x60 */
+
+  __IO uint32_t reserved_6; /* Not used. offset 0x64. */
+
+  /* TODO add the rest starting at offset 0x68. */
+
+} PACKED rcc_t;
+
+#define RCC (*(__IO rcc_t*) RCC_BASE)
+
+/* Macros to operate on the RCC registers. */
+
+/* Sets the HSE. rcc is the RCC to use, e is zero for off, non-zero for on. */
+#define set_hse(rcc, e) do \
+{ \
+  if (e) { \
+    (rcc).c_r |= 1 << 16; \
+  } else { \
+    (rcc).c_r &= ~(1 << 16); \
+  } \
+} while(0)
+
+/* Sets the HSI. rcc is the RCC to use, e is zero for off, non-zero for on. */
+#define set_hsi(rcc, e) do \
+{ \
+  if (e) { \
+    (rcc).c_r |= 1 << 8; \
+  } else { \
+    (rcc).c_r &= ~(1 << 8); \
+  } \
+} while(0)
+
+
+/* Checks to see if the hse is ready. */
+#define hse_ready(rcc) ((rcc).c_r & (1 << 17))
+
+/* Checks to see if the hse is ready. */
+#define hsi_ready(rcc) ((rcc).c_r & (1 << 10))
+
+#endif
diff --git a/system-clock/include/spin.h b/system-clock/include/spin.h
index a920847..a88d2f8 100644
--- a/system-clock/include/spin.h
+++ b/system-clock/include/spin.h
@@ -10,7 +10,7 @@
  * is a 0. Each independent flashing is succeced by a break of 4 times that
  * of a long flash.
  */
-void spin(uint8_t code);
+void spin(uint32_t base_delay, uint8_t code);