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| author | Josh Rahm <joshuarahm@gmail.com> | 2018-01-16 00:02:56 -0700 |
|---|---|---|
| committer | Josh Rahm <joshuarahm@gmail.com> | 2018-01-16 00:02:56 -0700 |
| commit | 92c50db2b05818157d46e09f4dec4fa1e96f960b (patch) | |
| tree | c264b9d183e9c69fb8434712347a5680a41edf3a /system-clock/src/gpio.c | |
| parent | 6d3197d768bf13c1402c1305050ea355f8c79fec (diff) | |
| download | stm32l4-92c50db2b05818157d46e09f4dec4fa1e96f960b.tar.gz stm32l4-92c50db2b05818157d46e09f4dec4fa1e96f960b.tar.bz2 stm32l4-92c50db2b05818157d46e09f4dec4fa1e96f960b.zip | |
able to set the clock speed in MHz.
Diffstat (limited to 'system-clock/src/gpio.c')
| -rw-r--r-- | system-clock/src/gpio.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/system-clock/src/gpio.c b/system-clock/src/gpio.c index ab3606d..f79f233 100644 --- a/system-clock/src/gpio.c +++ b/system-clock/src/gpio.c @@ -1,4 +1,5 @@ #include "gpio.h" +#include "rcc.h" /* * Sets the mode of a pin on a gpio por. @@ -38,11 +39,9 @@ void set_gpio_output_pin( } #define GPIO_PORTS_BASE_ADDR ((uint32_t)0x48000000) -#define RCC_BASE ((uint32_t)0x40021000) -#define RCC_AHB2ENR (*((__IO uint32_t*) (RCC_BASE + 0x4c))) __IO gpio_port_t* enable_gpio(gpio_port_number_t gpio_port_number) { - RCC_AHB2ENR |= 1 << gpio_port_number; /* Enable the port. */ + RCC.ahb2en_r |= 1 << gpio_port_number; /* Enable the GPIO port. */ return (__IO gpio_port_t*) (GPIO_PORTS_BASE_ADDR + (gpio_port_number * 0x400)); } |