diff options
author | Josh Rahm <joshuarahm@gmail.com> | 2018-01-22 00:14:20 -0700 |
---|---|---|
committer | Josh Rahm <joshuarahm@gmail.com> | 2018-01-22 00:14:20 -0700 |
commit | af0244fb51ccb608440128d0f3303ccce77c14c2 (patch) | |
tree | 4b6057fe3c3029ee4b4602e690917859c6011599 /usart/src/gpio.c | |
parent | 2dcbbea5fe1e2342ce4700b3ee8dce44a360a888 (diff) | |
download | stm32l4-af0244fb51ccb608440128d0f3303ccce77c14c2.tar.gz stm32l4-af0244fb51ccb608440128d0f3303ccce77c14c2.tar.bz2 stm32l4-af0244fb51ccb608440128d0f3303ccce77c14c2.zip |
VERY simple USART set up on USART2.
Diffstat (limited to 'usart/src/gpio.c')
-rw-r--r-- | usart/src/gpio.c | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/usart/src/gpio.c b/usart/src/gpio.c new file mode 100644 index 0000000..02933b7 --- /dev/null +++ b/usart/src/gpio.c @@ -0,0 +1,52 @@ +#include "gpio.h" +#include "rcc.h" + +/* + * Sets the mode of a pin on a gpio por. + */ +void set_gpio_pin_mode( + __IO gpio_port_t* gpio_port, gpio_pin_t pin, gpio_pin_mode_t mode) +{ + /* Each pin has a 2-bit mode provided at bits pin#*2 and pin#*2+1 */ + gpio_port->mode_r &= ~(0x03 << pin * 2); + gpio_port->mode_r |= mode << pin * 2; +} + +gpio_output_pin_t set_gpio_pin_output( + __IO gpio_port_t* gpio_port, gpio_pin_t pin) +{ + set_gpio_pin_mode(gpio_port, pin, MODE_OUTPUT); + + return (gpio_output_pin_t){.gpio_port = gpio_port, .pin = pin}; +} + +void set_gpio_output_pin(gpio_output_pin_t pin, bool onoff) +{ + if (onoff) { + pin.gpio_port->output_r |= 1 << pin.pin; + } else { + pin.gpio_port->output_r &= ~(1 << pin.pin); + } +} + +void set_gpio_alternate_function( + __IO gpio_port_t* port, gpio_pin_t gpio_pin, alternate_function_t afn) +{ + __IO uint32_t* reg; + if (gpio_pin < 8) { + reg = &(port->af_rl); + } else { + reg = &(port->af_rh); + gpio_pin -= 8; + } + + uint32_t tmp = *reg & (~0x0f << gpio_pin * 4); + *reg = tmp | (afn << gpio_pin * 4); +} + +#define GPIO_PORTS_BASE_ADDR ((uint8_t*)0x48000000) +__IO gpio_port_t* enable_gpio(gpio_port_number_t gpio_port_number) +{ + RCC.ahb2en_r |= 1 << gpio_port_number; /* Enable the GPIO port. */ + return (__IO gpio_port_t*)(GPIO_PORTS_BASE_ADDR + (gpio_port_number * 0x400)); +} |