diff options
Diffstat (limited to '03-refactor/src/clock.c')
| -rw-r--r-- | 03-refactor/src/clock.c | 35 |
1 files changed, 24 insertions, 11 deletions
diff --git a/03-refactor/src/clock.c b/03-refactor/src/clock.c index c4dcbac..7256500 100644 --- a/03-refactor/src/clock.c +++ b/03-refactor/src/clock.c @@ -61,8 +61,21 @@ int configure_pll( return E_BADPLLN; } - RCC.pllcfg_r = (pllp_div_factor << 27) | (pllr << 24) | (pllq << 20) | - (pllp << 16) | (plln << 8) | (pllm << 4) | (pllsrc << 0); + union RCC_PLLCFGR tmp; + + tmp.pllpdiv = pllp_div_factor; + tmp.pllr = pllr >> 1; + tmp.pllren = pllr & 1; + tmp.pllp = pllp >> 1; + tmp.pllpen = pllp & 1; + tmp.pllq = pllq >> 1; + tmp.pllqen = pllq & 1; + tmp.plln = plln; + tmp.pllm = pllm; + + tmp.pllsrc = pllsrc; + + RCC.pllcfg = tmp; return 0; } @@ -79,13 +92,13 @@ int set_system_clock_MHz(uint8_t mhz) pll_off(); configure_pll( - 0 /* pllp_div_factor */, PLL_DIVISOR_4 /* pllr: VCO / 4 = mhz MHz. */, - PLL_DIVISOR_4 /* pllq: VCO / 4 = mhz MHz */, PLLP_DIVISOR_7 /* pllp */, - - /* The following set the frequency of VCO to (mhz*4)MHz: mhz * 1 * 4MHz. - */ - mhz /* plln | mhz */, PLLM_DIVISOR_1 /* pllm | 01 */, - PLL_SRC_MSI /* pll src | 04 Mhz */); + 0, + PLL_DIVISOR_4, + PLL_DIVISOR_4, + PLLP_DIVISOR_7, + mhz, + PLLM_DIVISOR_1, + PLL_SRC_MSI); pll_on(); @@ -101,8 +114,8 @@ int set_system_clock_MHz(uint8_t mhz) int set_system_clock_src(system_clock_src_t src) { - uint8_t value = RCC.cfg_r & ~0x03; - RCC.cfg_r = value | src; + uint8_t value = RCC.cfg.r & ~0x03; + RCC.cfg.r = value | src; } int enable_hsi(__IO rcc_t* rcc, bool enable) |