diff options
| -rw-r--r-- | 02-usart/Makefile.preamble | 4 | ||||
| -rwxr-xr-x | 02-usart/genmake.pl | 22 | ||||
| -rw-r--r-- | 02-usart/include/arch/arm/arch.h | 20 | ||||
| -rw-r--r-- | 02-usart/include/arch/x86_64/arch.h | 19 | ||||
| -rw-r--r-- | 02-usart/include/common.h | 6 | ||||
| -rw-r--r-- | 02-usart/include/dma.h | 167 | ||||
| -rw-r--r-- | 02-usart/include/usart.h | 84 | ||||
| -rw-r--r-- | 02-usart/src/main.c | 5 | ||||
| -rw-r--r-- | 02-usart/src/usart.c | 12 | ||||
| -rw-r--r-- | 02-usart/test_harness/Makefile | 9 | ||||
| -rw-r--r-- | 02-usart/test_harness/fake_env.c | 25 | ||||
| -rw-r--r-- | 02-usart/test_harness/fake_env.h | 13 | ||||
| -rw-r--r-- | 02-usart/test_harness/test_harness.c | 82 | ||||
| -rw-r--r-- | 02-usart/test_harness/test_harness.h | 88 | ||||
| -rw-r--r-- | 02-usart/tests/test_dma.c | 27 |
15 files changed, 561 insertions, 22 deletions
diff --git a/02-usart/Makefile.preamble b/02-usart/Makefile.preamble index 3c8a61b..0dc02bb 100644 --- a/02-usart/Makefile.preamble +++ b/02-usart/Makefile.preamble @@ -2,9 +2,11 @@ OPT?=-O PREFIX?=arm-unknown-eabi- CC=$(PREFIX)gcc LD=$(PREFIX)ld -CFLAGS?=$(OPT) -mcpu=cortex-m4 -mthumb -g -lgcc -static -nostartfiles -Iinclude +CFLAGS?=$(OPT) -mcpu=cortex-m4 -mthumb -g -lgcc -static -nostartfiles -Iinclude -Iinclude/arch/arm LD_FLAGS?=-T linker/linker_script.ld -nostdlib --cref -Map linker/main.map -static +TEST_PREFIX=x86_64-pc-linux-gnu- +TEST_CFLAGS=-Iinclude -Iinclude/arch/x86_64 -Itest_harness -g3 -ggdb all: _$(PREFIX)_obs/main.elf diff --git a/02-usart/genmake.pl b/02-usart/genmake.pl index 341db3d..a0e99de 100755 --- a/02-usart/genmake.pl +++ b/02-usart/genmake.pl @@ -19,6 +19,7 @@ sub header_deps { } my @files = glob('src/*.c'); +my @test_files = glob('tests/*.c'); my @obj_files; open(my $fh, '<:encoding(UTF-8)', "Makefile.preamble") @@ -30,10 +31,10 @@ while (<$fh>) { # Emit a rule that will rerun genmake if the c files do not match. my $idempotency_cmd = - "ls src/*.c include/*.h| sha1sum | awk '{print \$1}'"; + "ls src/*.c include/*.h tests/*.c | sha1sum | awk '{print \$1}'"; my $idempotency_cmd_make = - "ls src/*.c include/*.h | sha1sum | awk '{print \$\$1}'"; + "ls src/*.c include/*.h tests/*.c | sha1sum | awk '{print \$\$1}'"; print "IDEMPOTENCY_HASH=" . `$idempotency_cmd` . "\n"; @@ -62,6 +63,23 @@ foreach $file (@files) { } my $obj_files_deps = join(' ', @obj_files); + +foreach $file (@test_files) { + my $c_file = $file; + (my $file_no_ext = $file) =~ s/(.*)\.c/\1/g; + my @deps = header_deps($c_file); + my $deps_as_join = join(" ", @deps); + + print "_${file_no_ext}: $deps_as_join $obj_files_deps test_harness/test_harness.a\n\t"; + print '$(CC) $(CFLAGS) -o' . $file_no_ext . ' ' . $c_file . ' ' . $obj_file_deps . " test_harness/test_harness.a\n\n"; + + print "${file_no_ext}: $deps_as_join $obj_files_deps test_harness/test_harness.a\n\t"; + print 'PREFIX=$(TEST_PREFIX) CFLAGS="$(TEST_CFLAGS)" $(MAKE) _' . $file_no_ext . "\n\n"; +} + +print "test_harness/test_harness.a: test_harness/test_harness.h test_harness/test_harness.c\n\t"; +print 'cd test_harness; $(MAKE) test_harness.a; cd ..' . "\n\n"; + print "FORCE:\n\t\n\n"; print "$arch_obs_dir/main.elf: FORCE $obj_files_deps linker/linker_script.ld\n\t"; print "([ \"\$\$($idempotency_cmd_make)\" != \"\$(IDEMPOTENCY_HASH)\" ] " diff --git a/02-usart/include/arch/arm/arch.h b/02-usart/include/arch/arm/arch.h new file mode 100644 index 0000000..904cbdb --- /dev/null +++ b/02-usart/include/arch/arm/arch.h @@ -0,0 +1,20 @@ +#ifndef ARCH_H_ +#define ARCH_H_ + + +#define ARCH_STM32L4 + +#define enable_interrupts() \ + asm volatile(" cpsie i ") + +#define DMA1_BASE (0x40020000) +#define DMA2_BASE (0x40020400) + +#define USART1_BASE (0x40013800) +#define USART2_BASE (0x40004400) + +#define GPIOA_BASE (0x48000000) +#define GPIOB_BASE (0x48000400) +#define GPIOC_BASE (0x48000800) + +#endif /* ARCH_H_ */ diff --git a/02-usart/include/arch/x86_64/arch.h b/02-usart/include/arch/x86_64/arch.h new file mode 100644 index 0000000..43f6077 --- /dev/null +++ b/02-usart/include/arch/x86_64/arch.h @@ -0,0 +1,19 @@ +#ifndef ARCH_H_ +#define ARCH_H_ + +#include "fake_env.h" + +#define ARCH_PC +#define enable_interrupts() do {} while(0) + +#define DMA1_BASE (load_fake_ahb1__() + 0x0) +#define DMA2_BASE (load_fake_ahb1__() + 0x400) + +#define USART1_BASE (load_fake_apb2__() + 0x3800) +#define USART2_BASE (load_fake_apb1__() + 0x4400) + +#define GPIOA_BASE (load_fake_ahb2__() + 0x0) +#define GPIOB_BASE (load_fake_ahb2__() + 0x400) +#define GPIOC_BASE (load_fake_ahb2__() + 0x800) + +#endif /* ARCH_H_ */ diff --git a/02-usart/include/common.h b/02-usart/include/common.h index 9d5c7cd..01b6a47 100644 --- a/02-usart/include/common.h +++ b/02-usart/include/common.h @@ -2,6 +2,12 @@ #define COMMON__H #include <stdint.h> +#include <stddef.h> +#include <assert.h> + +#ifndef static_assert +#define static_assert(a, b) +#endif /* Define __IO to be volatile if it's not already. */ #ifndef __IO diff --git a/02-usart/include/dma.h b/02-usart/include/dma.h new file mode 100644 index 0000000..57462f9 --- /dev/null +++ b/02-usart/include/dma.h @@ -0,0 +1,167 @@ +#ifndef DMA_H_ +#define DMA_H_ + +/* + * Header file for definining the DMA (Direct Memory Access). + * + * A DMA is used to perform data transfers between segments of memory + * or between memory and peripherals. + * + * There are 2 DMA's on the chip. Each with 7 channels. + */ + +#include "common.h" +#include <arch.h> +#include <stdint.h> + +#define DMA1 (* (dma_t*) DMA1_BASE) +#define DMA2 (* (dma_t*) DMA2_BASE) + +typedef enum { + DMA_SIZE_8_BITS = 0, + DMA_SIZE_16_BITS = 1, + DMA_SIZE_32_BITS = 2, +} dma_size_t; + +typedef enum { + DMA_PRIORITY_LEVEL_LOW = 0, + DMA_PRIORITY_LEVEL_MEDIUM = 1, + DMA_PRIORITY_LEVEL_HIGH = 2, + DMA_PRIORITY_LEVEL_VERY_HIGH = 3 +} dma_priority_level; + +typedef struct { + union { + uint32_t cc_r; + struct { + bits_t en:1; // channel enable + bits_t tcie:1; // transfer complete interrupt enable + bits_t htie:1; // half transfer interrupt enable + bits_t teie:1; // transfer error interrupt enable + bits_t dir:1; // data transfer direction + bits_t circ:1; // circular mode + bits_t pinc:1; // peripheral increment mode + bits_t minc:1; // memory increment mode + bits_t psize:2; // Peripheral size + bits_t msize:2; // Memory size + bits_t pl:2; // Priority level + bits_t mem2mem:1; // Memory to memory mode + bits_t reserved:17; + } PACKED cc_bf; + }; + + /* Number of data to transfer. */ + union { + uint32_t cndt_r; + struct { + uint16_t ndt; // Number of data to transfer. + uint16_t reserved; + } cndt_bf; + }; + + /* DMA channel peripheral address register. + * Defines a memory address if mem2mem is set. */ + uint32_t cpa_r; + + /* DMA channel memory address register. + * Defines another perpipheral address if peripheral-periphal mode is set. */ + uint32_t cma_r; + + uint32_t reserved; +} dma_channel_config_t; + +typedef struct { + // DMA Interrupt status register. + union { + uint32_t is_r; + struct { + bits_t gif1:1; // global interrupt flag for channel 1 + bits_t tcif1:1; // transfer complete (TC) flag for channel 1 + bits_t htif1:1; // half transfer (HT) flag for channel 1 + bits_t teif1:1; // transfer error (TE) flag for channel 1 + bits_t gif2:1; // global interrupt flag for channel 2 + bits_t tcif2:1; // transfer complete (TC) flag for channel 2 + bits_t htif2:1; // half transfer (HT) flag for channel 2 + bits_t teif2:1; // transfer error (TE) flag for channel 2 + bits_t gif3:1; // global interrupt flag for channel 3 + bits_t tcif3:1; // transfer complete (TC) flag for channel 3 + bits_t htif3:1; // half transfer (HT) flag for channel 3 + bits_t teif3:1; // transfer error (TE) flag for channel 3 + bits_t gif4:1; // global interrupt flag for channel 4 + bits_t tcif4:1; // transfer complete (TC) flag for channel 4 + bits_t htif4:1; // half transfer (HT) flag for channel 4 + bits_t teif4:1; // transfer error (TE) flag for channel 4 + bits_t gif5:1; // global interrupt flag for channel 5 + bits_t tcif5:1; // transfer complete (TC) flag for channel 5 + bits_t htif5:1; // half transfer (HT) flag for channel 5 + bits_t teif5:1; // transfer error (TE) flag for channel 5 + bits_t gif6:1; // global interrupt flag for channel 6 + bits_t tcif6:1; // transfer complete (TC) flag for channel 6 + bits_t htif6:1; // half transfer (HT) flag for channel 6 + bits_t teif6:1; // transfer error (TE) flag for channel 6 + bits_t gif7:1; // global interrupt flag for channel 7 + bits_t tcif7:1; // transfer complete (TC) flag for channel 7 + bits_t htif7:1; // half transfer (HT) flag for channel 7 + bits_t teif7:1; // transfer error (TE) flag for channel 7 + bits_t reserved:4; + } PACKED is_bf; + }; + + // DMA Interrupt flag clear register + union { + uint32_t ifc_r; + struct { + bits_t cgif1:1; // global interrupt flag clear for channel 1 + bits_t ctcif1:1; // transfer complete flag clear for channel 1 + bits_t chtif1:1; // half transfer flag clear for channel 1 + bits_t cteif1:1; // transfer error flag clear for channel 1 + bits_t cgif2:1; // global interrupt flag clear for channel 2 + bits_t ctcif2:1; // transfer complete flag clear for channel 2 + bits_t chtif2:1; // half transfer flag clear for channel 2 + bits_t cteif2:1; // transfer error flag clear for channel 2 + bits_t cgif3:1; // global interrupt flag clear for channel 3 + bits_t ctcif3:1; // transfer complete flag clear for channel 3 + bits_t chtif3:1; // half transfer flag clear for channel 3 + bits_t cteif3:1; // transfer error flag clear for channel 3 + bits_t cgif4:1; // global interrupt flag clear for channel 4 + bits_t ctcif4:1; // transfer complete flag clear for channel 4 + bits_t chtif4:1; // half transfer flag clear for channel 4 + bits_t cteif4:1; // transfer error flag clear for channel 4 + bits_t cgif5:1; // global interrupt flag clear for channel 5 + bits_t ctcif5:1; // transfer complete flag clear for channel 5 + bits_t chtif5:1; // half transfer flag clear for channel 5 + bits_t cteif5:1; // transfer error flag clear for channel 5 + bits_t cgif6:1; // global interrupt flag clear for channel 6 + bits_t ctcif6:1; // transfer complete flag clear for channel 6 + bits_t chtif6:1; // half transfer flag clear for channel 6 + bits_t cteif6:1; // transfer error flag clear for channel 6 + bits_t cgif7:1; // global interrupt flag clear for channel 7 + bits_t ctcif7:1; // transfer complete flag clear for channel 7 + bits_t chtif7:1; // half transfer flag clear for channel 7 + bits_t cteif7:1; // transfer error flag clear for channel 7 + } PACKED ifc_bf; + }; + + dma_channel_config_t channel_config[7]; + + uint32_t reserved[5]; + + /* DMA channel selection register. */ + union { + uint32_t csel_r; + struct { + bits_t c1s:4; // DMA channel 1 selection. + bits_t c2s:4; // DMA channel 2 selection. + bits_t c3s:4; // DMA channel 3 selection. + bits_t c4s:4; // DMA channel 4 selection. + bits_t c5s:4; // DMA channel 5 selection. + bits_t c6s:4; // DMA channel 6 selection. + bits_t c7s:4; // DMA channel 7 selection. + bits_t reserved:4; + } PACKED csel_bf; + }; +} dma_t; + +static_assert(offsetof(dma_t, csel_r) == 0xA8, "Offset check failed."); + +#endif /* DMA_H_ */ diff --git a/02-usart/include/usart.h b/02-usart/include/usart.h index 257aab6..d806397 100644 --- a/02-usart/include/usart.h +++ b/02-usart/include/usart.h @@ -1,13 +1,17 @@ #ifndef H__USART_ #define H__USART_ +#include <arch.h> +#include <stdint.h> + #include "common.h" #include "rcc.h" -#include <stdint.h> +#define USART1 (* (__IO usart_t*) USART1_BASE) +#define USART2 (* (__IO usart_t*) USART2_BASE) /* - * Possibel USART clock sources. + * Possible USART clock sources. */ typedef enum { USART_CLK_SRC_PLK = 0, /* Clock derived from the SysClk. */ @@ -43,24 +47,82 @@ typedef struct { bits_t eobie:1; bits_t m1:1; bits_t reserved:3; - } PACKED c1_bf; - }; + } PACKED c1_bf; /* c1_bf = c1 bit field */ + }; /* USART Control Register 1. */ uint32_t c_r2; - uint32_t c_r3; + + union { + uint32_t c_r3; + struct { + bits_t eie:1; // Error interrupt enable. + bits_t iren:1; // IrDA mode enabled + bits_t irlp:1; // IrDA low power + bits_t hdsel:1; // Half duplex selection + bits_t nack:1; // Smartcard NACK enable + bits_t scen:1; // Smartocard mode enable + bits_t dmar:1; // DMA enable reciever + bits_t dmat:1; // DMA enable transmitter + bits_t rtse:1; // RTS enable + bits_t ctse:1; // CTS enable + bits_t ctsie:1; // CTS interrupt enable + bits_t onebit:1; // One sample bit method enable + bits_t ovrdis:1; // Overrun disable + bits_t ddre:1; // DMA Disable on reception error + bits_t dem:1; // Driver enable mode + bits_t dep:1; // Driver enable polarity selection + bits_t reserved0:1; + bits_t scarcnt:3; // Smartcard auto-retry count. + bits_t wus:2; // Wakeup from STOP mode interrept flag selection + bits_t wufie:1; // Wakeup from STOP mode interrup enable + bits_t ucesm:1; // USART clock enable in STOP mode. + bits_t tcbgtie:1; // Transmission complete before guard time interrupt + bits_t reserved1:7; + } PACKED c3_bf; + }; /* USART baud rate register. */ uint32_t br_r; uint32_t gtp_r; uint32_t rto_r; uint32_t rq_r; - uint32_t is_r; + + /* USART ISR register. Offset = 0x1c*/ + union { + uint32_t is_r; /* Interrupt service register. */ + struct { + bits_t pe:1; // Parity error + bits_t fe:1; // Framing error + bits_t nf:1; // START bit noise detection flag. + bits_t ore:1; // Overrun error + bits_t dlie:1; // Idle line detected + bits_t rxne:1; // Read data register not empty + bits_t tc:1; // Transmission complete + bits_t txe:1; // Transmit data register empty + bits_t lbdf:1; // LIN break detection flag + bits_t ctsif:1; // CTS interrupt flag + bits_t cts:1; // CTS flag. + bits_t rtof:1; // Receiever timeout + bits_t eobf:1; // End of block flag + bits_t reserved0:1; + bits_t abre:1; // Auto baud rate error + bits_t abrf:1; // Auto baud rate flag + bits_t busy:1; // Busy flag + bits_t cmf:1; // Character match flag + bits_t sbkf:1; // send break flag + bits_t rwu:1; // receiver wakeup frlom mute mode. + bits_t wuf:1; // Wakeup from stop mode flag + bits_t teack:1; // Transmit enable acknowledge flag. + bits_t reack:1; // Receieve enable acknowledge flag. + bits_t reserved1:2; + bits_t tcbgt:1; // Transmission completer before guard time completion. + bits_t reserved2:6; + } PACKED is_bf; /* Interrupt servite bit field. */ + }; uint32_t ic_r; uint32_t rd_r; uint32_t td_r; } usart_t; -#define USART1 (* (__IO usart_t*) 0x40013800) -#define USART2 (* (__IO usart_t*) 0x40004400) typedef enum { OVERSAMPLE_8, OVERSAMPLE_16 @@ -112,7 +174,7 @@ void usart_set_enabled(__IO usart_t* usart, usart_enable_t enabled); * Send a byte on the usart, This command blocks until the data * is fully sent. */ -void usart_transmit_byte(__IO usart_t* usart, uint8_t byte); +void usart_transmit_byte_sync(__IO usart_t* usart, uint8_t byte); void set_usart1_clock_src(__IO rcc_t* rcc, usart_clk_src_t usart_clk_src); @@ -122,10 +184,10 @@ void set_usart2_clock_src(__IO rcc_t* rcc, usart_clk_src_t usart_clk_src); void set_usart2_clock_enabled(__IO rcc_t* rcc, bool enable); -void usart_transmit_bytes( +void usart_transmit_bytes_sync( __IO usart_t* usart, const uint8_t* bytes, uint32_t n); -void usart_transmit_str(__IO usart_t* usart, const char* str); +void usart_transmit_str_sync(__IO usart_t* usart, const char* str); #endif /* H__USART_ */ diff --git a/02-usart/src/main.c b/02-usart/src/main.c index 5af52ed..862676c 100644 --- a/02-usart/src/main.c +++ b/02-usart/src/main.c @@ -1,4 +1,5 @@ +#include "arch.h" #include "clock.h" #include "delay.h" #include "gpio.h" @@ -70,7 +71,7 @@ int enable_usart1(uint32_t baud_rate) /* Enable the transmitter and the receiver. */ usart_set_enabled(&USART1, USART_ENABLE_TX); - asm volatile(" cpsie i "); + enable_interrupts(); } /* Main function. This gets executed from the interrupt vector defined above. */ @@ -88,6 +89,6 @@ int main() enable_usart2(115200); pin_on(pin3); - usart_transmit_str(&USART2, "Hello, World\n"); + usart_transmit_str_sync(&USART2, "Hello, World\n"); for(;;); } diff --git a/02-usart/src/usart.c b/02-usart/src/usart.c index eddfbe7..42297a8 100644 --- a/02-usart/src/usart.c +++ b/02-usart/src/usart.c @@ -51,7 +51,7 @@ void usart_set_enabled(__IO usart_t* usart, usart_enable_t enabled) } } -void usart_transmit_byte(__IO usart_t* usart, uint8_t byte) +void usart_transmit_byte_sync(__IO usart_t* usart, uint8_t byte) { usart->td_r = byte; /* Per the manual, when bit 7 of the IS register is set, then the usart @@ -62,19 +62,19 @@ void usart_transmit_byte(__IO usart_t* usart, uint8_t byte) ; } -void usart_transmit_bytes(__IO usart_t* usart, const uint8_t* bytes, uint32_t n) +void usart_transmit_bytes_sync(__IO usart_t* usart, const uint8_t* bytes, uint32_t n) { while (n --) { - usart_transmit_byte(usart, *(bytes ++)); + usart_transmit_byte_sync(usart, *(bytes ++)); } } -void usart_transmit_str(__IO usart_t* usart, const char* str) +void usart_transmit_str_sync(__IO usart_t* usart, const char* str) { while (*str) { if (*str == '\n') { - usart_transmit_byte(usart, '\r'); + usart_transmit_byte_sync(usart, '\r'); } - usart_transmit_byte(usart, *(str ++)); + usart_transmit_byte_sync(usart, *(str ++)); } } diff --git a/02-usart/test_harness/Makefile b/02-usart/test_harness/Makefile new file mode 100644 index 0000000..443292b --- /dev/null +++ b/02-usart/test_harness/Makefile @@ -0,0 +1,9 @@ +CC=gcc +CFLAGS=-g3 -ggdb -Wall + +test_harness.a: test_harness.c test_harness.h fake_env.o + gcc -o test_harness.o -c test_harness.c $(CFLAGS) + ar r test_harness.a test_harness.o fake_env.o + +fake_env.o: fake_env.c fake_env.h + gcc -o fake_env.o -c fake_env.c $(CFLAGS) diff --git a/02-usart/test_harness/fake_env.c b/02-usart/test_harness/fake_env.c new file mode 100644 index 0000000..45cb1e9 --- /dev/null +++ b/02-usart/test_harness/fake_env.c @@ -0,0 +1,25 @@ +#include "fake_env.h" + +#include <stdlib.h> +#include <assert.h> + +#define DEFINE_MEMORY_SEGMENT(name, start_addr, end_addr) \ + static void* fake_##name = NULL; \ + void* load_fake_##name##__ () \ + { \ + if (fake_##name == NULL) { \ + fake_##name = malloc((end_addr) - (start_addr)); \ + assert(fake_##name != NULL); \ + } \ + return fake_##name; \ + } + +/* Peripheral buses */ +DEFINE_MEMORY_SEGMENT(apb1, 0x40000000, 0x40010000) +DEFINE_MEMORY_SEGMENT(apb2, 0x40010000, 0x40020000) +DEFINE_MEMORY_SEGMENT(ahb1, 0x40020000, 0x40024400) +DEFINE_MEMORY_SEGMENT(ahb2, 0x48000000, 0x50060C00) + +/* SRAM */ +DEFINE_MEMORY_SEGMENT(sram1, 0x20000000, 0x2000C000) +DEFINE_MEMORY_SEGMENT(sram2, 0x2000C000, 0x20018000) diff --git a/02-usart/test_harness/fake_env.h b/02-usart/test_harness/fake_env.h new file mode 100644 index 0000000..12c09ff --- /dev/null +++ b/02-usart/test_harness/fake_env.h @@ -0,0 +1,13 @@ +#ifndef FAKE_ENV_H_ +#define FAKE_ENV_H_ + +/* Functions which wil lazily load fake chunks of memory + * corresponding to the*/ +void* load_fake_ahb1__(); +void* load_fake_ahb2__(); +void* load_fake_apb1__(); +void* load_fake_apb2__(); +void* load_fake_sram1__(); +void* load_fake_sram2__(); + +#endif /* FAKE_ENV_H_ */ diff --git a/02-usart/test_harness/test_harness.c b/02-usart/test_harness/test_harness.c new file mode 100644 index 0000000..9f7dd79 --- /dev/null +++ b/02-usart/test_harness/test_harness.c @@ -0,0 +1,82 @@ +#include "test_harness.h" + +#include <assert.h> +#include <stdio.h> +#include <sys/types.h> +#include <sys/wait.h> +#include <unistd.h> +#include <stdlib.h> +#include <setjmp.h> + + +static jmp_buf jmpbuf; + +volatile test_t dummy + __attribute((__section__("tests"))) + __attribute((__used__)) = { + "dummy", + "dummy", + NULL +}; + +extern test_t __start_tests; +extern test_t __stop_tests; + +test_t* iter = &__start_tests; + +static int execute_test(test_t* test); + +int main() { + for( ; iter < &__stop_tests; ++ iter) { + if (iter->fn_ptr != NULL) { + execute_test(iter); + } + } +} + +void test_harness_abort(int ec) +{ + longjmp(jmpbuf, ec); + assert("Long jump failed.\n"); +} + +static int execute_test(test_t* test) +{ + char fullname[512]; + int status; + int ec; + pid_t pid; + const char* note = ""; + + snprintf( + fullname, sizeof(fullname), "%s::%s", iter->test_suite, iter->test_name); + + if (!(pid = fork())) { + // child + + if ((ec = setjmp(jmpbuf))) { + exit(ec); + } else { + test->fn_ptr(); + exit(0); + } + } else { + if (waitpid(pid, &status, 0) == -1) { + fprintf(stderr, "waitpid() failed\n"); + return 1; + } + + ec = WEXITSTATUS(status); + switch (ec) { + case 0: + printf("%s " GREEN "[PASS]" RESET "\n", fullname); + return 0; + case 11: + note = " (SIGSEGV)"; + break; + } + + printf("%s " RED "[FAIL] %d%s" RESET "\n", fullname, ec, note); + return ec; + } +} diff --git a/02-usart/test_harness/test_harness.h b/02-usart/test_harness/test_harness.h new file mode 100644 index 0000000..0a218f8 --- /dev/null +++ b/02-usart/test_harness/test_harness.h @@ -0,0 +1,88 @@ +#ifndef TEST_HARNESS_H_ +#define TEST_HARNESS_H_ + +#include <stdio.h> +#include <string.h> + +#define YELLOW "\x1b[00;33m" +#define GREEN "\x1b[01;32m" +#define RED "\x1b[01;31m" +#define RESET "\x1b[0m" + +typedef struct { + const char* test_suite; + const char* test_name; + int (*fn_ptr)(); + void* alignment; +} test_t; + +#define GENPR(fmt, v1, v2) \ + fprintf(stderr, fmt "\n", v1, v2) + +#define FORMAT_STRING(v1, v2) \ + _Pragma("GCC diagnostic push"); \ + _Pragma("GCC diagnostic ignored \"-Wpointer-to-int-cast\""); \ + _Generic(v1, long: GENPR("%ld == %ld", v1, v2), \ + unsigned long: GENPR("%lu == %lu", v1, v2), \ + int: GENPR("%d == %d", v1, v2), \ + unsigned int: GENPR("%u == %u", v1, v2), \ + short: GENPR("%h == %h", v1, v2), \ + unsigned short: GENPR("%hu == %hu", v1, v2), \ + char: GENPR("%c == %c", v1, v2), \ + double: GENPR("%f == %f", v1, v2), \ + unsigned char: fprintf( \ + stderr, "%02x == %02x\n", (unsigned int) v1, (unsigned int) v2),\ + default: GENPR("%p == %p\n", v1, v2)); \ + _Pragma("GCC diagnostic pop") + +#define TRY_PRINT_TYPE(v1, v2, type, fmt) \ + else if (__builtin_types_compatible_p(typeof (v1), type)) { \ + fprintf(stderr, fmt " == " fmt "\n", v1, v2); \ + } + +#define TYPE_STR(t) #t + +#define ASSERT_TRUE(x) \ + do { \ + if (!(x)) { \ + fprintf(stderr, RED "ASSERT_TRUE FAILED!\n" RESET); \ + fprintf(stderr, " - " YELLOW "In expression ASSERT_TRUE(" #x ")\n"); \ + fprintf(stderr, RESET " - " YELLOW "At " __FILE__ ":%d\n" RESET, __LINE__); \ + test_harness_abort(1); \ + } \ + } while (0) + +#define ASSERT_EQ(x, y) \ + do { \ + if ((x) != (y)) { \ + fprintf(stderr, RED "ASSERT_EQ FAILED! " RESET "Not true that "); \ + FORMAT_STRING(x, y); \ + fprintf(stderr, " - " YELLOW "In expression ASSERT_EQ(" #x ", " #y ")\n"); \ + fprintf(stderr, RESET " - " YELLOW "At " __FILE__ ":%d\n" RESET, __LINE__); \ + test_harness_abort(1); \ + } \ + } while (0) + +#define ASSERT_EQ_STR(x, y) \ + do { \ + if (strcmp(x, y)) { \ + fprintf(stderr, \ + RED "ASSSERT_EQ_STR FAILED! " RESET "Not true that \"%s\" equals \"%s\"", \ + x, y); \ + fprintf(stderr, " - " YELLOW "In expression ASSERT_EQ_STR(" #x ", " #y ")\n"); \ + fprintf(stderr, RESET " - " YELLOW "At " __FILE__":%d\n" RESET, __LINE__); \ + test_harness_abort(1); \ + } \ + } while (0) + + +#define TEST(test_suite, test_name) \ + int test_suite ## _ ## test_name ## _fn (void); \ + volatile test_t test_suite ## _ ## test_name ## _testing_struct__ \ + __attribute((__section__("tests"))) __attribute((__used__)) = \ + {#test_suite, #test_name, test_suite ## _ ## test_name ## _fn}; \ + int test_suite ## _ ## test_name ## _fn (void) + +void test_harness_abort(int ec); + +#endif diff --git a/02-usart/tests/test_dma.c b/02-usart/tests/test_dma.c new file mode 100644 index 0000000..7c2127a --- /dev/null +++ b/02-usart/tests/test_dma.c @@ -0,0 +1,27 @@ +#include "test_harness.h" +#include "dma.h" + +#include <stdio.h> +#include <stdlib.h> +#include <memory.h> + +TEST(dma, smoke) { + dma_t* dma = &DMA1; + memset(dma, sizeof(dma), 0); + + dma->is_bf.tcif1 = 1; + ASSERT_EQ(dma->is_r, 2); + + dma->is_bf.htif7 = 1; + ASSERT_EQ(dma->is_r, 67108866); +} + +TEST(dma, correct_align) +{ + dma_t dma; + + // Assert the DMA registers are aligned with what the spec says. + ASSERT_EQ((long)(&dma.csel_r) - (long)(&dma), 0xA8); + + return 0; +} |