diff options
| -rw-r--r-- | .clang-format | 7 | ||||
| -rw-r--r-- | hello/main.c | 279 | ||||
| -rw-r--r-- | system-clock/include/clock.h | 49 | ||||
| -rw-r--r-- | system-clock/include/flash.h | 4 | ||||
| -rw-r--r-- | system-clock/include/gpio.h | 44 | ||||
| -rw-r--r-- | system-clock/include/isr_vector.h | 1 | ||||
| -rw-r--r-- | system-clock/include/rcc.h | 71 | ||||
| -rw-r--r-- | system-clock/include/spin.h | 2 | ||||
| -rw-r--r-- | system-clock/src/clock.c | 53 | ||||
| -rw-r--r-- | system-clock/src/delay.c | 4 | ||||
| -rw-r--r-- | system-clock/src/gpio.c | 22 | ||||
| -rw-r--r-- | system-clock/src/isr_vector.c | 214 | ||||
| -rw-r--r-- | system-clock/src/main.c | 8 | ||||
| -rw-r--r-- | system-clock/src/spin.c | 10 |
14 files changed, 363 insertions, 405 deletions
diff --git a/.clang-format b/.clang-format new file mode 100644 index 0000000..6c15953 --- /dev/null +++ b/.clang-format @@ -0,0 +1,7 @@ +BasedOnStyle: Google +IndentWidth: 2 +BreakBeforeBraces: Custom +BraceWrapping: + AfterFunction: true +AllowShortFunctionsOnASingleLine: InlineOnly +AlignAfterOpenBracket: AlwaysBreak diff --git a/hello/main.c b/hello/main.c index ccec59c..fe2b9d5 100644 --- a/hello/main.c +++ b/hello/main.c @@ -10,115 +10,114 @@ void spin(); * Interrupt service routine handlers. */ const void* vectors[] __attribute__((section(".vectors"))) = { - (void *) 0x2000c000, /* Top of stack at top of sram1. 48k */ - main, /* Reset handler */ - spin, /* NMI */ - spin, /* Hard Fault */ - spin, /* MemManage */ - spin, /* BusFault */ - spin, /* UsageFault */ - spin, /* Reserved */ - spin, /* Reserved */ - spin, /* Reserved */ - spin, /* Reserved */ - spin, /* SVCall */ - spin, /* Debug */ - spin, /* Reserved */ - spin, /* PendSV */ - spin, /* SysTick */ - -/* External interrupt handlers follow */ - spin, /* 0 WWDG */ - spin, /* 1 PVD */ - spin, /* 2 TAMP_SAMP */ - spin, /* 3 RTC_WKUP */ - spin, /* 4 FLASH */ - spin, /* 5 RCC */ - spin, /* 6 EXTI0 */ - spin, /* 7 EXTI1 */ - spin, /* 8 EXTI2 */ - spin, /* 9 EXTI3 */ - spin, /* 10 EXTI4 */ - spin, /* 11 DMA_CH1 */ - spin, /* 12 DMA_CH2 */ - spin, /* 13 DMA_CH3 */ - spin, /* 14 DMA_CH4 */ - spin, /* 15 DMA_CH5 */ - spin, /* 16 DMA_CH6 */ - spin, /* 17 DMA_CH7 */ - spin, /* 18 ADC1 */ - spin, /* 19 CAN_TX */ - spin, /* 20 CAN_RX0 */ - spin, /* 21 CAN_RX1 */ - spin, /* 22 CAN_SCE */ - spin, /* 23 EXTI9_5 */ - spin, /* 24 TIM1_BRK/TIM15 */ - spin, /* 25 TIM1_UP/TIM16 */ - spin, /* 26 TIM1_TRG_COM */ - spin, /* 27 TIM1_CC */ - spin, /* 28 TIM2 */ - spin, /* 29 Reserved */ - spin, /* 30 Reserved */ - spin, /* 31 I2C1_EV */ - spin, /* 32 I2C1_ER */ - spin, /* 33 I2C2_EV */ - spin, /* 34 I2C2_ER */ - spin, /* 35 SPI1 */ - spin, /* 36 SPI2 */ - spin, /* 37 USART1 */ - spin, /* 38 USART2 */ - spin, /* 39 USART3 */ - spin, /* 40 EXTI15_10 */ - spin, /* 41 RTCAlarm */ - spin, /* 42 Reserved */ - spin, /* 43 Reserved */ - spin, /* 44 Reserved */ - spin, /* 45 Reserved */ - spin, /* 46 Reserved */ - spin, /* 47 Reserved */ - spin, /* 48 Reserved */ - spin, /* 49 SDMMC1 */ - spin, /* 50 Reserved */ - spin, /* 51 SPI3 */ - spin, /* 52 Reserved */ - spin, /* 53 Reserved */ - spin, /* 54 TIM6_DACUNDER */ - spin, /* 55 TIM7 */ - spin, /* 56 DMA2_CH1 */ - spin, /* 57 DMA2_CH2 */ - spin, /* 58 DMA2_CH3 */ - spin, /* 59 DMA2_CH4 */ - spin, /* 60 DMA2_CH5 */ - spin, /* 61 Reserved */ - spin, /* 62 Reserved */ - spin, /* 63 Reserved*/ - spin, /* 64 COMP */ - spin, /* 65 LPTIM1 */ - spin, /* 66 LPTIM2 */ - spin, /* 67 USB_FS */ - spin, /* 68 DMA_CH6 */ - spin, /* 69 DMA_CH7 */ - spin, /* 70 LPUART1 */ - spin, /* 71 QUADSPI */ - spin, /* 72 I2C3_EV */ - spin, /* 73 I2C3_ER */ - spin, /* 74 SAI1 */ - spin, /* 75 Reserved */ - spin, /* 76 SWPMI1 */ - spin, /* 77 TSC */ - spin, /* 78 Reserved */ - spin, /* 79 AES */ - spin, /* 80 RNG */ - spin, /* 81 FPU */ - spin /* 82 CRS */ + (void*)0x2000c000, /* Top of stack at top of sram1. 48k */ + main, /* Reset handler */ + spin, /* NMI */ + spin, /* Hard Fault */ + spin, /* MemManage */ + spin, /* BusFault */ + spin, /* UsageFault */ + spin, /* Reserved */ + spin, /* Reserved */ + spin, /* Reserved */ + spin, /* Reserved */ + spin, /* SVCall */ + spin, /* Debug */ + spin, /* Reserved */ + spin, /* PendSV */ + spin, /* SysTick */ + + /* External interrupt handlers follow */ + spin, /* 0 WWDG */ + spin, /* 1 PVD */ + spin, /* 2 TAMP_SAMP */ + spin, /* 3 RTC_WKUP */ + spin, /* 4 FLASH */ + spin, /* 5 RCC */ + spin, /* 6 EXTI0 */ + spin, /* 7 EXTI1 */ + spin, /* 8 EXTI2 */ + spin, /* 9 EXTI3 */ + spin, /* 10 EXTI4 */ + spin, /* 11 DMA_CH1 */ + spin, /* 12 DMA_CH2 */ + spin, /* 13 DMA_CH3 */ + spin, /* 14 DMA_CH4 */ + spin, /* 15 DMA_CH5 */ + spin, /* 16 DMA_CH6 */ + spin, /* 17 DMA_CH7 */ + spin, /* 18 ADC1 */ + spin, /* 19 CAN_TX */ + spin, /* 20 CAN_RX0 */ + spin, /* 21 CAN_RX1 */ + spin, /* 22 CAN_SCE */ + spin, /* 23 EXTI9_5 */ + spin, /* 24 TIM1_BRK/TIM15 */ + spin, /* 25 TIM1_UP/TIM16 */ + spin, /* 26 TIM1_TRG_COM */ + spin, /* 27 TIM1_CC */ + spin, /* 28 TIM2 */ + spin, /* 29 Reserved */ + spin, /* 30 Reserved */ + spin, /* 31 I2C1_EV */ + spin, /* 32 I2C1_ER */ + spin, /* 33 I2C2_EV */ + spin, /* 34 I2C2_ER */ + spin, /* 35 SPI1 */ + spin, /* 36 SPI2 */ + spin, /* 37 USART1 */ + spin, /* 38 USART2 */ + spin, /* 39 USART3 */ + spin, /* 40 EXTI15_10 */ + spin, /* 41 RTCAlarm */ + spin, /* 42 Reserved */ + spin, /* 43 Reserved */ + spin, /* 44 Reserved */ + spin, /* 45 Reserved */ + spin, /* 46 Reserved */ + spin, /* 47 Reserved */ + spin, /* 48 Reserved */ + spin, /* 49 SDMMC1 */ + spin, /* 50 Reserved */ + spin, /* 51 SPI3 */ + spin, /* 52 Reserved */ + spin, /* 53 Reserved */ + spin, /* 54 TIM6_DACUNDER */ + spin, /* 55 TIM7 */ + spin, /* 56 DMA2_CH1 */ + spin, /* 57 DMA2_CH2 */ + spin, /* 58 DMA2_CH3 */ + spin, /* 59 DMA2_CH4 */ + spin, /* 60 DMA2_CH5 */ + spin, /* 61 Reserved */ + spin, /* 62 Reserved */ + spin, /* 63 Reserved*/ + spin, /* 64 COMP */ + spin, /* 65 LPTIM1 */ + spin, /* 66 LPTIM2 */ + spin, /* 67 USB_FS */ + spin, /* 68 DMA_CH6 */ + spin, /* 69 DMA_CH7 */ + spin, /* 70 LPUART1 */ + spin, /* 71 QUADSPI */ + spin, /* 72 I2C3_EV */ + spin, /* 73 I2C3_ER */ + spin, /* 74 SAI1 */ + spin, /* 75 Reserved */ + spin, /* 76 SWPMI1 */ + spin, /* 77 TSC */ + spin, /* 78 Reserved */ + spin, /* 79 AES */ + spin, /* 80 RNG */ + spin, /* 81 FPU */ + spin /* 82 CRS */ }; - typedef struct { __IO uint32_t value; } rcc_reg_t; -#define RCC_AHB2ENR (*((__IO rcc_reg_t*) (RCC_BASE_2 + 0x4c))) +#define RCC_AHB2ENR (*((__IO rcc_reg_t*)(RCC_BASE_2 + 0x4c))) typedef enum { GPIO_PORT_A = 0, @@ -133,16 +132,16 @@ void enable_gpio(gpio_port_number_t port) } typedef enum { - PIN_0 = 0, - PIN_1 = 1, - PIN_2 = 2, - PIN_3 = 3, - PIN_4 = 4, - PIN_5 = 5, - PIN_6 = 6, - PIN_7 = 7, - PIN_8 = 8, - PIN_9 = 9, + PIN_0 = 0, + PIN_1 = 1, + PIN_2 = 2, + PIN_3 = 3, + PIN_4 = 4, + PIN_5 = 5, + PIN_6 = 6, + PIN_7 = 7, + PIN_8 = 8, + PIN_9 = 9, PIN_10 = 10, PIN_11 = 11, PIN_12 = 12, @@ -152,10 +151,10 @@ typedef enum { } pin_t; typedef enum { - MODE_INPUT = 0, - MODE_OUTPUT = 1, + MODE_INPUT = 0, + MODE_OUTPUT = 1, MODE_ALTERNATE = 2, - MODE_ANALOG = 3 + MODE_ANALOG = 3 } pin_mode_t; /* GPIO port speed. */ @@ -179,7 +178,6 @@ typedef struct { __IO uint32_t value; } __attribute__((packed)) type_reg_t; - /* * Speed register. Allows low, meduim, fast or high speed. */ @@ -187,9 +185,8 @@ typedef struct { __IO uint32_t value; } __attribute__((packed)) speed_reg_t; - /* - * Pull up/pull down register. Allows pull up, pull down, or no pull up or + * Pull up/pull down register. Allows pull up, pull down, or no pull up or * pull down. */ typedef struct { @@ -234,36 +231,35 @@ typedef struct { __IO uint32_t value_low; } __attribute__((packed)) alt_function_reg_t; - /* Structure defining the layout of a GPIO port on the STM32L432. */ typedef struct { - __IO mode_reg_t mode; /* Mode register */ - __IO pull_reg_t pupd; /* Pull up/pull down/none register */ - __IO speed_reg_t speed; /* Speed register */ - __IO type_reg_t type; /* Type register */ - __IO input_data_reg_t input; /* Input data register */ - __IO output_data_reg_t output; /* Output data register */ - __IO bit_set_reset_reg_t bsr; /* Bit set/reset register */ - __IO lock_reg_t lock; /* Lock register */ - __IO alt_function_reg_t altfn; /* Alternate function registers */ + __IO mode_reg_t mode; /* Mode register */ + __IO pull_reg_t pupd; /* Pull up/pull down/none register */ + __IO speed_reg_t speed; /* Speed register */ + __IO type_reg_t type; /* Type register */ + __IO input_data_reg_t input; /* Input data register */ + __IO output_data_reg_t output; /* Output data register */ + __IO bit_set_reset_reg_t bsr; /* Bit set/reset register */ + __IO lock_reg_t lock; /* Lock register */ + __IO alt_function_reg_t altfn; /* Alternate function registers */ } __attribute__((packed)) gpio_port_t; /* * Defines for GPIO memory mapped addresses. */ -#define GPIO_A (*((__IO gpio_port_t*) 0x48000000)) -#define GPIO_B (*((__IO gpio_port_t*) 0x48000400)) -#define GPIO_C (*((__IO gpio_port_t*) 0x48000800)) +#define GPIO_A (*((__IO gpio_port_t*)0x48000000)) +#define GPIO_B (*((__IO gpio_port_t*)0x48000400)) +#define GPIO_C (*((__IO gpio_port_t*)0x48000800)) /* * Delays for `delay` iterations. */ void delay(uint32_t delay) { - while(delay --) { + while (delay--) { // Empty volatile assembly to keep the optimizer from getting // rid of this loop entirely. - asm volatile (""); + asm volatile(""); } } @@ -275,9 +271,7 @@ void delay(uint32_t delay) * pin_mode: the mode of the pin. See pin_mode_t enum. */ void set_gpio_pin_mode( - __IO gpio_port_t* gpio_port, - uint32_t pin, - pin_mode_t pin_mode) + __IO gpio_port_t* gpio_port, uint32_t pin, pin_mode_t pin_mode) { gpio_port->mode.value &= ~(0x03 << pin * 2); gpio_port->mode.value |= pin_mode << pin * 2; @@ -290,10 +284,7 @@ void set_gpio_pin_mode( * pin: the number of the pin to enable. Values 0-15 * val: 0 to set the gpio pin to low, non-zero to set to high. */ -void set_gpio_pin( - __IO gpio_port_t* gpio_port, - uint32_t pin, - int val) +void set_gpio_pin(__IO gpio_port_t* gpio_port, uint32_t pin, int val) { if (val) { gpio_port->output.value |= 1 << pin; @@ -302,7 +293,6 @@ void set_gpio_pin( } } - /* Main function. This gets executed from the interrupt vector defined above. */ int main() { @@ -313,7 +303,7 @@ int main() set_gpio_pin_mode(&GPIO_B, /* pin = */ 3, MODE_OUTPUT); set_gpio_pin_mode(&GPIO_B, /* pin = */ 1, MODE_OUTPUT); - while(1) { + while (1) { /* Set the GPIO pin to high. */ set_gpio_pin(&GPIO_B, /* pin = */ 3, 1); set_gpio_pin(&GPIO_B, /* pin = */ 1, 0); @@ -349,8 +339,7 @@ int main() */ void spin() { - for(;;) { - + for (;;) { /* Flash in a distinct pattern to know that something went wrong. */ set_gpio_pin(&GPIO_B, /* pin = */ 3, 0); diff --git a/system-clock/include/clock.h b/system-clock/include/clock.h index 98574d1..de4fb96 100644 --- a/system-clock/include/clock.h +++ b/system-clock/include/clock.h @@ -4,12 +4,11 @@ #include <stdint.h> #include "rcc.h" -#define PERIPH_BASE ((uint32_t) 0x40000000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000) -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00) -#define PWR_BASE (PERIPH_BASE + 0x7000) -#define PWR_CSR_VOSF ((uint16_t)0x0010) /*!< Voltage Scaling select flag */ - +#define PERIPH_BASE ((uint32_t)0x40000000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00) +#define PWR_BASE (PERIPH_BASE + 0x7000) +#define PWR_CSR_VOSF ((uint16_t)0x0010) /*!< Voltage Scaling select flag */ #ifndef __IO #define __IO volatile @@ -29,26 +28,25 @@ typedef struct { // __IO uint32_t optkeyr; // __IO uint32_t sr; // __IO uint32_t obr; -// __IO uint32_t wrpr; +// __IO uint32_t wrpr; // } flash_t; // #define FLASH (*(flash_t*) (FLASH_R_BASE)) -#define PWR (*(pwr_t*) (PWR_BASE)) - +#define PWR (*(pwr_t*)(PWR_BASE)) /* Valid values for the PLLR/PLLQ bits of the PLLCFG register. */ typedef enum { - PLL_DIVISOR_2 = 1, - PLL_DIVISOR_4 = 3, - PLL_DIVISOR_6 = 5, - PLL_DIVISOR_8 = 7, + PLL_DIVISOR_2 = 1, + PLL_DIVISOR_4 = 3, + PLL_DIVISOR_6 = 5, + PLL_DIVISOR_8 = 7, PLL_DIVISOR_OFF = 0, } pll_divisor_t; /* Valid values for the PLLP bits off the PLLCFG register. */ -typedef enum { - PLLP_DIVISOR_7 = 1, - PLLP_DIVISOR_17 = 3, +typedef enum { + PLLP_DIVISOR_7 = 1, + PLLP_DIVISOR_17 = 3, PLLP_DIVISOR_OFF = 0, } pllp_divisor_t; @@ -67,9 +65,9 @@ typedef enum { /* Possible sources for the input clock. */ typedef enum { PLL_SRC_NONE = 0, - PLL_SRC_MSI = 1, - PLL_SRC_HSI = 2, - PLL_SRC_HSE = 3, + PLL_SRC_MSI = 1, + PLL_SRC_HSI = 2, + PLL_SRC_HSE = 3, } pll_src_t; /* Valid sources for the system clock. */ @@ -110,12 +108,11 @@ int set_system_clock_src(system_clock_src_t src); * Configure the PLL. */ int configure_pll( - uint8_t pllp_div_factor, - pll_divisor_t pllr, /* System clock divisor. */ - pll_divisor_t pllq, /* Divison factor for PLL48M1CLK. */ - pllp_divisor_t pllp, /* Divison factor for PLLSAI2CLK. */ - uint8_t plln, /* PLL numerator. */ - pllm_divisor_t pllm, /* PLL denominator. */ - pll_src_t pllsrc /* PLL source */ ); + uint8_t pllp_div_factor, pll_divisor_t pllr, /* System clock divisor. */ + pll_divisor_t pllq, /* Divison factor for PLL48M1CLK. */ + pllp_divisor_t pllp, /* Divison factor for PLLSAI2CLK. */ + uint8_t plln, /* PLL numerator. */ + pllm_divisor_t pllm, /* PLL denominator. */ + pll_src_t pllsrc /* PLL source */); #endif /* CLOCK_H__ */ diff --git a/system-clock/include/flash.h b/system-clock/include/flash.h index ac63bf9..a163a25 100644 --- a/system-clock/include/flash.h +++ b/system-clock/include/flash.h @@ -7,7 +7,7 @@ * Header file for dealing with flash. */ -#define FLASH_BASE 0x40022000 +#define FLASH_BASE 0x40022000 typedef struct { __IO uint32_t ac_r; /* Flash access control register. */ @@ -15,6 +15,6 @@ typedef struct { /* TODO fill out the rest. */ } PACKED flash_t; -#define FLASH (*(__IO flash_t*) FLASH_BASE) +#define FLASH (*(__IO flash_t*)FLASH_BASE) #endif /* H__FLASH_ */ diff --git a/system-clock/include/gpio.h b/system-clock/include/gpio.h index 53ece32..a8f06e2 100644 --- a/system-clock/include/gpio.h +++ b/system-clock/include/gpio.h @@ -36,16 +36,16 @@ typedef struct GPIO_PORT_STR { * the stm32l432. */ typedef enum GPIO_PIN_ENUM { - PIN_0 = 0, - PIN_1 = 1, - PIN_2 = 2, - PIN_3 = 3, - PIN_4 = 4, - PIN_5 = 5, - PIN_6 = 6, - PIN_7 = 7, - PIN_8 = 8, - PIN_9 = 9, + PIN_0 = 0, + PIN_1 = 1, + PIN_2 = 2, + PIN_3 = 3, + PIN_4 = 4, + PIN_5 = 5, + PIN_6 = 6, + PIN_7 = 7, + PIN_8 = 8, + PIN_9 = 9, PIN_10 = 10, PIN_11 = 11, PIN_12 = 12, @@ -58,10 +58,10 @@ typedef enum GPIO_PIN_ENUM { * Enum defining the pin modes that are possible. */ typedef enum { - MODE_INPUT = 0, - MODE_OUTPUT = 1, + MODE_INPUT = 0, + MODE_OUTPUT = 1, MODE_ALTERNATE = 2, - MODE_ANALOG = 3 + MODE_ANALOG = 3 } gpio_pin_mode_t; /* @@ -90,17 +90,14 @@ typedef struct { * pin_mode: the mode to set the pin to. */ void set_gpio_pin_mode( - __IO gpio_port_t* gpio_port, - gpio_pin_t pin, - gpio_pin_mode_t pin_mode); + __IO gpio_port_t* gpio_port, gpio_pin_t pin, gpio_pin_mode_t pin_mode); /* * Sets the given GPIO pin to be an output pin. Returns an output_pin struct * corresponding to */ gpio_output_pin_t set_gpio_pin_output( - __IO gpio_port_t* gpio_port, - gpio_pin_t pin); + __IO gpio_port_t* gpio_port, gpio_pin_t pin); /* * Sets an output pin on or off. @@ -108,15 +105,11 @@ gpio_output_pin_t set_gpio_pin_output( * pin: the pin to toggle. * onoff: 0 for off, non-zero of on. */ -void set_gpio_output_pin( - gpio_output_pin_t pin, - bool onoff); +void set_gpio_output_pin(gpio_output_pin_t pin, bool onoff); -#define pin_on(p) \ - set_gpio_output_pin(p, 1) +#define pin_on(p) set_gpio_output_pin(p, 1) -#define pin_off(p) \ - set_gpio_output_pin(p, 0) +#define pin_off(p) set_gpio_output_pin(p, 0) /* * Enables a GPIO port and returns a reference to the register definition @@ -124,5 +117,4 @@ void set_gpio_output_pin( */ __IO gpio_port_t* enable_gpio(gpio_port_number_t number); - #endif /* GPIO_H__ */ diff --git a/system-clock/include/isr_vector.h b/system-clock/include/isr_vector.h index eee1a51..3e55f52 100644 --- a/system-clock/include/isr_vector.h +++ b/system-clock/include/isr_vector.h @@ -11,7 +11,6 @@ */ extern const void* isr_vector[]; - /* * Defines an error state. This loops forever and defines a distinct flashing * pattern to let the user know an unhandled ISR happened. diff --git a/system-clock/include/rcc.h b/system-clock/include/rcc.h index 4206dc1..4eeb26b 100644 --- a/system-clock/include/rcc.h +++ b/system-clock/include/rcc.h @@ -3,26 +3,26 @@ #include "common.h" -#define RCC_BASE ((uint32_t) 0x40021000) +#define RCC_BASE ((uint32_t)0x40021000) typedef struct { - __IO uint32_t c_r; /* Clock control register. 0x00 */ - __IO uint32_t icsc_r; /* Internal clock srcs calibration register. 0x04 */ - __IO uint32_t cfg_r; /* clock confguration register. 0x08 */ - __IO uint32_t pllcfg_r; /* PLL Configuration register. 0x0c */ - __IO uint32_t pllsai1cfg_r; /* PLLSAI1 configuration register. 0x10 */ + __IO uint32_t c_r; /* Clock control register. 0x00 */ + __IO uint32_t icsc_r; /* Internal clock srcs calibration register. 0x04 */ + __IO uint32_t cfg_r; /* clock confguration register. 0x08 */ + __IO uint32_t pllcfg_r; /* PLL Configuration register. 0x0c */ + __IO uint32_t pllsai1cfg_r; /* PLLSAI1 configuration register. 0x10 */ __IO uint32_t reserved_1; /* Not used. offset 0x14. */ - __IO uint32_t cie_r; /* Clock interrupt enable register. 0x18 */ - __IO uint32_t cif_r; /* Clock interrupt flag regiseter. 0x1c */ - __IO uint32_t cic_r; /* Clock interrupt clear register. 0x20 */ + __IO uint32_t cie_r; /* Clock interrupt enable register. 0x18 */ + __IO uint32_t cif_r; /* Clock interrupt flag regiseter. 0x1c */ + __IO uint32_t cic_r; /* Clock interrupt clear register. 0x20 */ __IO uint32_t reserved_2; /* Not used. offset 0x24. */ - __IO uint32_t ahb1rst_r; /* AHB Peripheral 1 reset register. 0x28 */ - __IO uint32_t ahb2rst_r; /* AHB Peripheral 2 reset register. 0x2c */ - __IO uint32_t ahb3rst_r; /* AHB Peripheral 3 reset register. 0x30 */ + __IO uint32_t ahb1rst_r; /* AHB Peripheral 1 reset register. 0x28 */ + __IO uint32_t ahb2rst_r; /* AHB Peripheral 2 reset register. 0x2c */ + __IO uint32_t ahb3rst_r; /* AHB Peripheral 3 reset register. 0x30 */ __IO uint32_t reserved_3; /* Not used. offset 0x34. */ @@ -32,15 +32,15 @@ typedef struct { __IO uint32_t reserved_4; /* Not used. offset 0x44. */ - __IO uint32_t ahb1en_r; /* AHB1 Peripheral enable register. 0x48 */ - __IO uint32_t ahb2en_r; /* AHB2 Peripheral enable register. 0x4C */ - __IO uint32_t ahb3en_r; /* AHB3 Peripheral enable register. 0x50 */ + __IO uint32_t ahb1en_r; /* AHB1 Peripheral enable register. 0x48 */ + __IO uint32_t ahb2en_r; /* AHB2 Peripheral enable register. 0x4C */ + __IO uint32_t ahb3en_r; /* AHB3 Peripheral enable register. 0x50 */ __IO uint32_t reserved_5; /* Not used. offset 0x54. */ - __IO uint32_t apb1en1_r; /* APB1 Peripheral enable register 1. 0x58 */ - __IO uint32_t apb1en2_r; /* APB1 Peripheral enable register 2. 0x5C */ - __IO uint32_t apb2en_r; /* APB2 Peripheral enable register. 0x60 */ + __IO uint32_t apb1en1_r; /* APB1 Peripheral enable register 1. 0x58 */ + __IO uint32_t apb1en2_r; /* APB1 Peripheral enable register 2. 0x5C */ + __IO uint32_t apb2en_r; /* APB2 Peripheral enable register. 0x60 */ __IO uint32_t reserved_6; /* Not used. offset 0x64. */ @@ -48,30 +48,29 @@ typedef struct { } PACKED rcc_t; -#define RCC (*(__IO rcc_t*) RCC_BASE) +#define RCC (*(__IO rcc_t*)RCC_BASE) /* Macros to operate on the RCC registers. */ /* Sets the HSE. rcc is the RCC to use, e is zero for off, non-zero for on. */ -#define set_hse(rcc, e) do \ -{ \ - if (e) { \ - (rcc).c_r |= 1 << 16; \ - } else { \ - (rcc).c_r &= ~(1 << 16); \ - } \ -} while(0) +#define set_hse(rcc, e) \ + do { \ + if (e) { \ + (rcc).c_r |= 1 << 16; \ + } else { \ + (rcc).c_r &= ~(1 << 16); \ + } \ + } while (0) /* Sets the HSI. rcc is the RCC to use, e is zero for off, non-zero for on. */ -#define set_hsi(rcc, e) do \ -{ \ - if (e) { \ - (rcc).c_r |= 1 << 8; \ - } else { \ - (rcc).c_r &= ~(1 << 8); \ - } \ -} while(0) - +#define set_hsi(rcc, e) \ + do { \ + if (e) { \ + (rcc).c_r |= 1 << 8; \ + } else { \ + (rcc).c_r &= ~(1 << 8); \ + } \ + } while (0) /* Checks to see if the hse is ready. */ #define hse_ready(rcc) ((rcc).c_r & (1 << 17)) diff --git a/system-clock/include/spin.h b/system-clock/include/spin.h index a88d2f8..a23d25b 100644 --- a/system-clock/include/spin.h +++ b/system-clock/include/spin.h @@ -12,6 +12,4 @@ */ void spin(uint32_t base_delay, uint8_t code); - - #endif /* H__SPIN_ */ diff --git a/system-clock/src/clock.c b/system-clock/src/clock.c index dd37684..75bac97 100644 --- a/system-clock/src/clock.c +++ b/system-clock/src/clock.c @@ -3,10 +3,10 @@ */ #include "clock.h" +#include <stdint.h> +#include "flash.h" #include "gpio.h" #include "spin.h" -#include "flash.h" -#include <stdint.h> #define TIMEOUT 10000 @@ -15,8 +15,9 @@ int pll_off() uint32_t c; RCC.c_r &= ~BIT(24); /* Turn off pll. */ - for(c = 0; c < TIMEOUT && RCC.c_r & BIT(25); ++ c); /* Wait for OFF. */ - + for (c = 0; c < TIMEOUT && RCC.c_r & BIT(25); ++c) + ; /* Wait for OFF. */ + if (c == TIMEOUT) { return E_TIMEOUT; } @@ -29,7 +30,8 @@ int pll_on() uint32_t c; RCC.c_r |= BIT(24); /* Turn on PLL. */ - for(c = 0; c < TIMEOUT && !(RCC.c_r & BIT(25)); ++ c); /* Wait for RDY. */ + for (c = 0; c < TIMEOUT && !(RCC.c_r & BIT(25)); ++c) + ; /* Wait for RDY. */ if (c == TIMEOUT) { return E_TIMEOUT; @@ -39,13 +41,12 @@ int pll_on() } int configure_pll( - uint8_t pllp_div_factor, - pll_divisor_t pllr, /* System clock divisor. */ - pll_divisor_t pllq, /* Divison factor for PLL48M1CLK. */ - pllp_divisor_t pllp, /* Divison factor for PLLSAI2CLK. */ - uint8_t plln, /* PLL numerator. */ - pllm_divisor_t pllm, /* PLL denominator. */ - pll_src_t pllsrc /* PLL source */ ) + uint8_t pllp_div_factor, pll_divisor_t pllr, /* System clock divisor. */ + pll_divisor_t pllq, /* Divison factor for PLL48M1CLK. */ + pllp_divisor_t pllp, /* Divison factor for PLLSAI2CLK. */ + uint8_t plln, /* PLL numerator. */ + pllm_divisor_t pllm, /* PLL denominator. */ + pll_src_t pllsrc /* PLL source */) { if (RCC.c_r & BIT(25)) { /* PLL must be off to configure it. */ @@ -60,18 +61,12 @@ int configure_pll( return E_BADPLLN; } - RCC.pllcfg_r = - (pllp_div_factor << 27) | - (pllr << 24) | - (pllq << 20) | - (pllp << 16) | - (plln << 8) | - (pllm << 4) | - (pllsrc << 0); + RCC.pllcfg_r = (pllp_div_factor << 27) | (pllr << 24) | (pllq << 20) | + (pllp << 16) | (plln << 8) | (pllm << 4) | (pllsrc << 0); return 0; } - + int set_system_clock_MHz(uint8_t mhz) { /* Set the source of the system colck to MSI temporarily. */ @@ -84,15 +79,13 @@ int set_system_clock_MHz(uint8_t mhz) pll_off(); configure_pll( - 0 /* pllp_div_factor */, - PLL_DIVISOR_4 /* pllr: VCO / 4 = mhz MHz. */, - PLL_DIVISOR_4 /* pllq: VCO / 4 = mhz MHz */, - PLLP_DIVISOR_7 /* pllp */, - - /* The following set the frequency of VCO to (mhz*4)MHz: mhz * 1 * 4MHz. */ - mhz /* plln | mhz */, - PLLM_DIVISOR_1 /* pllm | 01 */, - PLL_SRC_MSI /* pll src | 04 Mhz */); + 0 /* pllp_div_factor */, PLL_DIVISOR_4 /* pllr: VCO / 4 = mhz MHz. */, + PLL_DIVISOR_4 /* pllq: VCO / 4 = mhz MHz */, PLLP_DIVISOR_7 /* pllp */, + + /* The following set the frequency of VCO to (mhz*4)MHz: mhz * 1 * 4MHz. + */ + mhz /* plln | mhz */, PLLM_DIVISOR_1 /* pllm | 01 */, + PLL_SRC_MSI /* pll src | 04 Mhz */); pll_on(); diff --git a/system-clock/src/delay.c b/system-clock/src/delay.c index 077d1ff..2a16d47 100644 --- a/system-clock/src/delay.c +++ b/system-clock/src/delay.c @@ -2,8 +2,8 @@ void delay(uint32_t delay) { - while (delay --) { + while (delay--) { /* needed to keep the compiler from optimizing away the loop. */ - asm volatile (""); + asm volatile(""); } } diff --git a/system-clock/src/gpio.c b/system-clock/src/gpio.c index f79f233..2404398 100644 --- a/system-clock/src/gpio.c +++ b/system-clock/src/gpio.c @@ -5,31 +5,22 @@ * Sets the mode of a pin on a gpio por. */ void set_gpio_pin_mode( - __IO gpio_port_t* gpio_port, - gpio_pin_t pin, - gpio_pin_mode_t mode) + __IO gpio_port_t* gpio_port, gpio_pin_t pin, gpio_pin_mode_t mode) { /* Each pin has a 2-bit mode provided at bits pin#*2 and pin#*2+1 */ gpio_port->mode_r &= ~(0x03 << pin * 2); gpio_port->mode_r |= mode << pin * 2; } - gpio_output_pin_t set_gpio_pin_output( - __IO gpio_port_t* gpio_port, - gpio_pin_t pin) + __IO gpio_port_t* gpio_port, gpio_pin_t pin) { set_gpio_pin_mode(gpio_port, pin, MODE_OUTPUT); - return (gpio_output_pin_t) { - .gpio_port = gpio_port, - .pin = pin - }; + return (gpio_output_pin_t){.gpio_port = gpio_port, .pin = pin}; } -void set_gpio_output_pin( - gpio_output_pin_t pin, - bool onoff) +void set_gpio_output_pin(gpio_output_pin_t pin, bool onoff) { if (onoff) { pin.gpio_port->output_r |= 1 << pin.pin; @@ -38,10 +29,9 @@ void set_gpio_output_pin( } } -#define GPIO_PORTS_BASE_ADDR ((uint32_t)0x48000000) +#define GPIO_PORTS_BASE_ADDR ((uint32_t)0x48000000) __IO gpio_port_t* enable_gpio(gpio_port_number_t gpio_port_number) { RCC.ahb2en_r |= 1 << gpio_port_number; /* Enable the GPIO port. */ - return - (__IO gpio_port_t*) (GPIO_PORTS_BASE_ADDR + (gpio_port_number * 0x400)); + return (__IO gpio_port_t*)(GPIO_PORTS_BASE_ADDR + (gpio_port_number * 0x400)); } diff --git a/system-clock/src/isr_vector.c b/system-clock/src/isr_vector.c index dd7fea9..674a6bb 100644 --- a/system-clock/src/isr_vector.c +++ b/system-clock/src/isr_vector.c @@ -1,10 +1,9 @@ #include "isr_vector.h" -#include "gpio.h" #include "delay.h" +#include "gpio.h" /* Forward-declare the main function. This is implemented in main.c. */ -void main(); - +void main(); /* These are defined in the linker script. */ extern uint32_t INIT_DATA_VALUES; @@ -13,7 +12,6 @@ extern uint32_t DATA_SEGMENT_STOP; extern uint32_t BSS_START; extern uint32_t BSS_END; - /* * Runs before main. Initializes the data and bss segments by loading them * into memory. @@ -28,122 +26,121 @@ void init() /* Copy the values from flash into the data segment. */ while (dest != &DATA_SEGMENT_STOP) { - *(dest ++) = *(src ++); + *(dest++) = *(src++); } /* Everything in the BSS segment is set to zero. */ dest = &BSS_START; while (dest != &BSS_END) { - *(dest ++) = 0; + *(dest++) = 0; } - /* Jump to main. */ main(); } const void* vectors[] __attribute__((section(".vectors"))) = { - (void *) 0x2000c000, /* Top of stack at top of sram1. 48k */ - init, /* Reset handler */ - unhandled_isr, /* NMI */ - unhandled_isr, /* Hard Fault */ - unhandled_isr, /* MemManage */ - unhandled_isr, /* BusFault */ - unhandled_isr, /* UsageFault */ - unhandled_isr, /* Reserved */ - unhandled_isr, /* Reserved */ - unhandled_isr, /* Reserved */ - unhandled_isr, /* Reserved */ - unhandled_isr, /* SVCall */ - unhandled_isr, /* Debug */ - unhandled_isr, /* Reserved */ - unhandled_isr, /* PendSV */ - unhandled_isr, /* SysTick */ + (void*)0x2000c000, /* Top of stack at top of sram1. 48k */ + init, /* Reset handler */ + unhandled_isr, /* NMI */ + unhandled_isr, /* Hard Fault */ + unhandled_isr, /* MemManage */ + unhandled_isr, /* BusFault */ + unhandled_isr, /* UsageFault */ + unhandled_isr, /* Reserved */ + unhandled_isr, /* Reserved */ + unhandled_isr, /* Reserved */ + unhandled_isr, /* Reserved */ + unhandled_isr, /* SVCall */ + unhandled_isr, /* Debug */ + unhandled_isr, /* Reserved */ + unhandled_isr, /* PendSV */ + unhandled_isr, /* SysTick */ - /* External interrupt handlers follow */ - unhandled_isr, /* 0 WWDG */ - unhandled_isr, /* 1 PVD */ - unhandled_isr, /* 2 TAMP_SAMP */ - unhandled_isr, /* 3 RTC_WKUP */ - unhandled_isr, /* 4 FLASH */ - unhandled_isr, /* 5 RCC */ - unhandled_isr, /* 6 EXTI0 */ - unhandled_isr, /* 7 EXTI1 */ - unhandled_isr, /* 8 EXTI2 */ - unhandled_isr, /* 9 EXTI3 */ - unhandled_isr, /* 10 EXTI4 */ - unhandled_isr, /* 11 DMA_CH1 */ - unhandled_isr, /* 12 DMA_CH2 */ - unhandled_isr, /* 13 DMA_CH3 */ - unhandled_isr, /* 14 DMA_CH4 */ - unhandled_isr, /* 15 DMA_CH5 */ - unhandled_isr, /* 16 DMA_CH6 */ - unhandled_isr, /* 17 DMA_CH7 */ - unhandled_isr, /* 18 ADC1 */ - unhandled_isr, /* 19 CAN_TX */ - unhandled_isr, /* 20 CAN_RX0 */ - unhandled_isr, /* 21 CAN_RX1 */ - unhandled_isr, /* 22 CAN_SCE */ - unhandled_isr, /* 23 EXTI9_5 */ - unhandled_isr, /* 24 TIM1_BRK/TIM15 */ - unhandled_isr, /* 25 TIM1_UP/TIM16 */ - unhandled_isr, /* 26 TIM1_TRG_COM */ - unhandled_isr, /* 27 TIM1_CC */ - unhandled_isr, /* 28 TIM2 */ - unhandled_isr, /* 29 Reserved */ - unhandled_isr, /* 30 Reserved */ - unhandled_isr, /* 31 I2C1_EV */ - unhandled_isr, /* 32 I2C1_ER */ - unhandled_isr, /* 33 I2C2_EV */ - unhandled_isr, /* 34 I2C2_ER */ - unhandled_isr, /* 35 SPI1 */ - unhandled_isr, /* 36 SPI2 */ - unhandled_isr, /* 37 USART1 */ - unhandled_isr, /* 38 USART2 */ - unhandled_isr, /* 39 USART3 */ - unhandled_isr, /* 40 EXTI15_10 */ - unhandled_isr, /* 41 RTCAlarm */ - unhandled_isr, /* 42 Reserved */ - unhandled_isr, /* 43 Reserved */ - unhandled_isr, /* 44 Reserved */ - unhandled_isr, /* 45 Reserved */ - unhandled_isr, /* 46 Reserved */ - unhandled_isr, /* 47 Reserved */ - unhandled_isr, /* 48 Reserved */ - unhandled_isr, /* 49 SDMMC1 */ - unhandled_isr, /* 50 Reserved */ - unhandled_isr, /* 51 SPI3 */ - unhandled_isr, /* 52 Reserved */ - unhandled_isr, /* 53 Reserved */ - unhandled_isr, /* 54 TIM6_DACUNDER */ - unhandled_isr, /* 55 TIM7 */ - unhandled_isr, /* 56 DMA2_CH1 */ - unhandled_isr, /* 57 DMA2_CH2 */ - unhandled_isr, /* 58 DMA2_CH3 */ - unhandled_isr, /* 59 DMA2_CH4 */ - unhandled_isr, /* 60 DMA2_CH5 */ - unhandled_isr, /* 61 Reserved */ - unhandled_isr, /* 62 Reserved */ - unhandled_isr, /* 63 Reserved*/ - unhandled_isr, /* 64 COMP */ - unhandled_isr, /* 65 LPTIM1 */ - unhandled_isr, /* 66 LPTIM2 */ - unhandled_isr, /* 67 USB_FS */ - unhandled_isr, /* 68 DMA_CH6 */ - unhandled_isr, /* 69 DMA_CH7 */ - unhandled_isr, /* 70 LPUART1 */ - unhandled_isr, /* 71 QUADSPI */ - unhandled_isr, /* 72 I2C3_EV */ - unhandled_isr, /* 73 I2C3_ER */ - unhandled_isr, /* 74 SAI1 */ - unhandled_isr, /* 75 Reserved */ - unhandled_isr, /* 76 SWPMI1 */ - unhandled_isr, /* 77 TSC */ - unhandled_isr, /* 78 Reserved */ - unhandled_isr, /* 79 AES */ - unhandled_isr, /* 80 RNG */ - unhandled_isr, /* 81 FPU */ - unhandled_isr /* 82 CRS */ + /* External interrupt handlers follow */ + unhandled_isr, /* 0 WWDG */ + unhandled_isr, /* 1 PVD */ + unhandled_isr, /* 2 TAMP_SAMP */ + unhandled_isr, /* 3 RTC_WKUP */ + unhandled_isr, /* 4 FLASH */ + unhandled_isr, /* 5 RCC */ + unhandled_isr, /* 6 EXTI0 */ + unhandled_isr, /* 7 EXTI1 */ + unhandled_isr, /* 8 EXTI2 */ + unhandled_isr, /* 9 EXTI3 */ + unhandled_isr, /* 10 EXTI4 */ + unhandled_isr, /* 11 DMA_CH1 */ + unhandled_isr, /* 12 DMA_CH2 */ + unhandled_isr, /* 13 DMA_CH3 */ + unhandled_isr, /* 14 DMA_CH4 */ + unhandled_isr, /* 15 DMA_CH5 */ + unhandled_isr, /* 16 DMA_CH6 */ + unhandled_isr, /* 17 DMA_CH7 */ + unhandled_isr, /* 18 ADC1 */ + unhandled_isr, /* 19 CAN_TX */ + unhandled_isr, /* 20 CAN_RX0 */ + unhandled_isr, /* 21 CAN_RX1 */ + unhandled_isr, /* 22 CAN_SCE */ + unhandled_isr, /* 23 EXTI9_5 */ + unhandled_isr, /* 24 TIM1_BRK/TIM15 */ + unhandled_isr, /* 25 TIM1_UP/TIM16 */ + unhandled_isr, /* 26 TIM1_TRG_COM */ + unhandled_isr, /* 27 TIM1_CC */ + unhandled_isr, /* 28 TIM2 */ + unhandled_isr, /* 29 Reserved */ + unhandled_isr, /* 30 Reserved */ + unhandled_isr, /* 31 I2C1_EV */ + unhandled_isr, /* 32 I2C1_ER */ + unhandled_isr, /* 33 I2C2_EV */ + unhandled_isr, /* 34 I2C2_ER */ + unhandled_isr, /* 35 SPI1 */ + unhandled_isr, /* 36 SPI2 */ + unhandled_isr, /* 37 USART1 */ + unhandled_isr, /* 38 USART2 */ + unhandled_isr, /* 39 USART3 */ + unhandled_isr, /* 40 EXTI15_10 */ + unhandled_isr, /* 41 RTCAlarm */ + unhandled_isr, /* 42 Reserved */ + unhandled_isr, /* 43 Reserved */ + unhandled_isr, /* 44 Reserved */ + unhandled_isr, /* 45 Reserved */ + unhandled_isr, /* 46 Reserved */ + unhandled_isr, /* 47 Reserved */ + unhandled_isr, /* 48 Reserved */ + unhandled_isr, /* 49 SDMMC1 */ + unhandled_isr, /* 50 Reserved */ + unhandled_isr, /* 51 SPI3 */ + unhandled_isr, /* 52 Reserved */ + unhandled_isr, /* 53 Reserved */ + unhandled_isr, /* 54 TIM6_DACUNDER */ + unhandled_isr, /* 55 TIM7 */ + unhandled_isr, /* 56 DMA2_CH1 */ + unhandled_isr, /* 57 DMA2_CH2 */ + unhandled_isr, /* 58 DMA2_CH3 */ + unhandled_isr, /* 59 DMA2_CH4 */ + unhandled_isr, /* 60 DMA2_CH5 */ + unhandled_isr, /* 61 Reserved */ + unhandled_isr, /* 62 Reserved */ + unhandled_isr, /* 63 Reserved*/ + unhandled_isr, /* 64 COMP */ + unhandled_isr, /* 65 LPTIM1 */ + unhandled_isr, /* 66 LPTIM2 */ + unhandled_isr, /* 67 USB_FS */ + unhandled_isr, /* 68 DMA_CH6 */ + unhandled_isr, /* 69 DMA_CH7 */ + unhandled_isr, /* 70 LPUART1 */ + unhandled_isr, /* 71 QUADSPI */ + unhandled_isr, /* 72 I2C3_EV */ + unhandled_isr, /* 73 I2C3_ER */ + unhandled_isr, /* 74 SAI1 */ + unhandled_isr, /* 75 Reserved */ + unhandled_isr, /* 76 SWPMI1 */ + unhandled_isr, /* 77 TSC */ + unhandled_isr, /* 78 Reserved */ + unhandled_isr, /* 79 AES */ + unhandled_isr, /* 80 RNG */ + unhandled_isr, /* 81 FPU */ + unhandled_isr /* 82 CRS */ }; /* @@ -153,8 +150,7 @@ void unhandled_isr() { __IO gpio_port_t* port_b = enable_gpio(GPIO_PORT_B); gpio_output_pin_t pin3 = set_gpio_pin_output(port_b, PIN_3); - for(;;) { - + for (;;) { /* Flash in a distinct pattern to know that something went wrong. */ pin_off(pin3); diff --git a/system-clock/src/main.c b/system-clock/src/main.c index 39f4a80..7912bf2 100644 --- a/system-clock/src/main.c +++ b/system-clock/src/main.c @@ -1,6 +1,6 @@ -#include "gpio.h" -#include "delay.h" #include "clock.h" +#include "delay.h" +#include "gpio.h" #include "spin.h" volatile uint32_t delay_amt = 20000000 / 4; @@ -18,7 +18,7 @@ int main() set_system_clock_MHz(80); uint32_t count = 0; - while(1) { + while (1) { /* Set the GPIO pin to high. */ pin_off(pin1); pin_off(pin3); @@ -31,6 +31,6 @@ int main() pin_on(pin3); delay(delay_amt); - ++ count; + ++count; } } diff --git a/system-clock/src/spin.c b/system-clock/src/spin.c index f17f678..fbd16b6 100644 --- a/system-clock/src/spin.c +++ b/system-clock/src/spin.c @@ -1,13 +1,12 @@ #include "spin.h" -#include "gpio.h" #include "delay.h" +#include "gpio.h" #define SHORT_DELAY 200000 -#define LONG_DELAY (SHORT_DELAY * 2) +#define LONG_DELAY (SHORT_DELAY * 2) static void flash_bit( - uint32_t base, - gpio_output_pin_t out_pin, + uint32_t base, gpio_output_pin_t out_pin, uint8_t bit /* 0 => 0, non-zero => 1 */) { pin_on(out_pin); @@ -26,7 +25,7 @@ void spin(uint32_t base, uint8_t c) __IO gpio_port_t* port_b = enable_gpio(GPIO_PORT_B); gpio_output_pin_t pin3 = set_gpio_pin_output(port_b, PIN_3); - for(;;) { + for (;;) { code = c; flash_bit(base, pin3, code & 0x80); code <<= 1; @@ -36,7 +35,6 @@ void spin(uint32_t base, uint8_t c) code <<= 1; flash_bit(base, pin3, code & 0x80); - code <<= 1; flash_bit(base, pin3, code & 0x80); code <<= 1; |