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-rw-r--r--include/arch/stm32l4xxx/peripherals/rcc.h93
1 files changed, 55 insertions, 38 deletions
diff --git a/include/arch/stm32l4xxx/peripherals/rcc.h b/include/arch/stm32l4xxx/peripherals/rcc.h
index de7b568..65b2e86 100644
--- a/include/arch/stm32l4xxx/peripherals/rcc.h
+++ b/include/arch/stm32l4xxx/peripherals/rcc.h
@@ -1,9 +1,10 @@
#ifndef H__RCC_
#define H__RCC_
+#include <stdint.h>
+
#include "arch.h"
#include "kern/common.h"
-#include <stdint.h>
typedef struct {
__IO uint32_t c_r; /* Clock control register. 0x00 */
@@ -26,51 +27,54 @@ typedef struct {
__IO uint32_t reserved_3; /* Not used. offset 0x34. */
-#define rcc_lptim1rst (1 << 31) // Low Power Timer 1 reset
-#define rcc_opamprst (1 << 30) // OPAMP interface reset
-#define rcc_dac1rst (1 << 29) // DAC1 interface reset
-#define rcc_pwrrst (1 << 28) // Power interface reset
-#define rcc_can2rst (1 << 26) // CAN2 reset (this bit is reserved for STM32L47x/L48x devices)
-#define rcc_can1rst (1 << 25) // CAN1 reset
-#define rcc_crsrst (1 << 24) // CRS reset (this bit is reserved for STM32L47x/L48x devices)
-#define rcc_i2c3rst (1 << 23) // I2C3 reset
-#define rcc_i2c2rst (1 << 22) // I2C2 reset
-#define rcc_i2c1rst (1 << 21) // I2C1 reset
-#define rcc_uart5rst (1 << 20) // UART5 reset
-#define rcc_uart4rst (1 << 19) // UART4 reset
-#define rcc_usart3rst (1 << 18) // USART3 reset
-#define rcc_usart2rst (1 << 17) // USART2 reset
-#define rcc_reserved (1 << 16) // must be kept at reset value.
-#define rcc_spi3rst (1 << 15) // SPI3 reset
-#define rcc_spi2rst (1 << 14) // SPI2 reset
-#define rcc_lcdrst (1 << 9) // interface reset (this bit is reserved for STM32L471/L4x5 devices)
-#define rcc_tim7rst (1 << 5) // timer reset
-#define rcc_tim6rst (1 << 4) // timer reset
-#define rcc_tim5rst (1 << 3) // timer reset
-#define rcc_tim4rst (1 << 2) // timer reset
-#define rcc_tim3rst (1 << 1) // timer reset
-#define rcc_tim2rst (1 << 0) // timer reset
+#define rcc_lptim1rst (1 << 31) // Low Power Timer 1 reset
+#define rcc_opamprst (1 << 30) // OPAMP interface reset
+#define rcc_dac1rst (1 << 29) // DAC1 interface reset
+#define rcc_pwrrst (1 << 28) // Power interface reset
+#define rcc_can2rst \
+ (1 << 26) // CAN2 reset (this bit is reserved for STM32L47x/L48x devices)
+#define rcc_can1rst (1 << 25) // CAN1 reset
+#define rcc_crsrst \
+ (1 << 24) // CRS reset (this bit is reserved for STM32L47x/L48x devices)
+#define rcc_i2c3rst (1 << 23) // I2C3 reset
+#define rcc_i2c2rst (1 << 22) // I2C2 reset
+#define rcc_i2c1rst (1 << 21) // I2C1 reset
+#define rcc_uart5rst (1 << 20) // UART5 reset
+#define rcc_uart4rst (1 << 19) // UART4 reset
+#define rcc_usart3rst (1 << 18) // USART3 reset
+#define rcc_usart2rst (1 << 17) // USART2 reset
+#define rcc_reserved (1 << 16) // must be kept at reset value.
+#define rcc_spi3rst (1 << 15) // SPI3 reset
+#define rcc_spi2rst (1 << 14) // SPI2 reset
+#define rcc_lcdrst \
+ (1 << 9) // interface reset (this bit is reserved for STM32L471/L4x5 devices)
+#define rcc_tim7rst (1 << 5) // timer reset
+#define rcc_tim6rst (1 << 4) // timer reset
+#define rcc_tim5rst (1 << 3) // timer reset
+#define rcc_tim4rst (1 << 2) // timer reset
+#define rcc_tim3rst (1 << 1) // timer reset
+#define rcc_tim2rst (1 << 0) // timer reset
__IO uint32_t apb1rst1_r; /* APB Peripheral reset register 1. 0x38 */
__IO uint32_t apb1rst2_r; /* APB Peripheral reset register 2. 0x3C */
__IO uint32_t apb2rst_r; /* APB Peripheral reset register. 0x40 */
__IO uint32_t reserved_4; /* Not used. offset 0x44. */
-#define rcc_dma1en (1 << 0) /* DMA1 clock enable. */
-#define rcc_dma2en (1 << 1) /* DMA2 clock enable. */
-#define rcc_flashen (1 << 8) /* Flash memory interface clock enable. */
-#define rcc_crcen (1 << 12) /* CRC clock enable. */
-#define rcc_tscen (1 << 16) /* Touch sensing controller clock enable. */
+#define rcc_dma1en (1 << 0) /* DMA1 clock enable. */
+#define rcc_dma2en (1 << 1) /* DMA2 clock enable. */
+#define rcc_flashen (1 << 8) /* Flash memory interface clock enable. */
+#define rcc_crcen (1 << 12) /* CRC clock enable. */
+#define rcc_tscen (1 << 16) /* Touch sensing controller clock enable. */
#define rcc_dmad2en (1 << 17) /* DMA2D clock enabled. */
__IO uint32_t ahb1en_r; /* AHB1 Peripheral enable register. 0x48 */
-#define rcc_gpioen(port) (1 << (port))
-#define rcc_otgfsen (1 << 12)
-#define rcc_adcen (1 << 13)
-#define rcc_dcmien (1 << 14)
-#define rcc_assen (1 << 16)
-#define rcc_hashen (1 << 17)
-#define rcc_rngen (1 << 18)
+#define rcc_gpioen(port) (1 << (port))
+#define rcc_otgfsen (1 << 12)
+#define rcc_adcen (1 << 13)
+#define rcc_dcmien (1 << 14)
+#define rcc_assen (1 << 16)
+#define rcc_hashen (1 << 17)
+#define rcc_rngen (1 << 18)
__IO uint32_t ahb2en_r; /* AHB2 Peripheral enable register. 0x4C */
__IO uint32_t ahb3en_r; /* AHB3 Peripheral enable register. 0x50 */
@@ -78,7 +82,20 @@ typedef struct {
__IO uint32_t apb1en1_r; /* APB1 Peripheral enable register 1. 0x58 */
__IO uint32_t apb1en2_r; /* APB1 Peripheral enable register 2. 0x5C */
- __IO uint32_t apb2en_r; /* APB2 Peripheral enable register. 0x60 */
+#define rcc_syscfgen (1 << 0)
+#define rcc_fwen (1 << 7)
+#define rcc_sdmmc1en (1 << 10)
+#define rcc_tim1en (1 << 11)
+#define rcc_spi1en (1 << 12)
+#define rcc_tim8en (1 << 13)
+#define rcc_usart1en (1 << 14)
+#define rcc_tim15en (1 << 16)
+#define rcc_tim16en (1 << 17)
+#define rcc_tim17en (1 << 18)
+#define rcc_sai1en (1 << 21)
+#define rcc_sai2en (1 << 22)
+#define rcc_dfsdm1en (1 << 24)
+ __IO uint32_t apb2en_r; /* APB2 Peripheral enable register. 0x60 */
__IO uint32_t reserved_6; /* Not used. offset 0x64. */