diff options
Diffstat (limited to 'system-clock/src/clock.c')
| -rw-r--r-- | system-clock/src/clock.c | 230 |
1 files changed, 116 insertions, 114 deletions
diff --git a/system-clock/src/clock.c b/system-clock/src/clock.c index b846ceb..ec12240 100644 --- a/system-clock/src/clock.c +++ b/system-clock/src/clock.c @@ -3,147 +3,149 @@ */ #include "clock.h" +#include "gpio.h" +#include "spin.h" +#include "flash.h" #include <stdint.h> -#define RCC_CR_HSERDY ((uint32_t)0x00020000) /* High-speed clock ready? */ -#define RCC_CR_HSEON ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ - -#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< Latency */ -#define FLASH_ACR_PRFTEN ((uint32_t)0x00000002) /*!< Prefetch Buffer Enable */ -#define FLASH_ACR_ACC64 ((uint32_t)0x00000004) /*!< Access 64 bits */ - -#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ -#define PWR_CR_VOS_0 ((uint16_t)0x0800) /*!< Bit 0 */ - -/*!< HPRE configuration */ -#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ -#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ -#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ -#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ -#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ -#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ -#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ -#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ -#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ - -#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ -#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ - -/*!< PPRE1 configuration */ -#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ - -#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ -#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ -#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ -#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ - -/*!< PPRE2 configuration */ -#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ -#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ -#define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000) /*!< PLLDIV[1:0] bits (PLL Output Division) */ - -#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ -#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE as PLL entry clock source */ -#define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000) /*!< PLL input clock * 8 */ -#define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000) /*!< PLL clock output = CKVCO / 2 */ -#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */ -#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */ -#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ -#define RCC_CFGR_SW_PLL ((uint32_t)0x00000003) /*!< PLL selected as system clock */ -#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ -#define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000C) /*!< PLL used as system clock */ - -inline int is_hse_ready() +#define TIMEOUT 10000 + +int pll_off() { - return RCC.cr & RCC_CR_HSERDY; + uint32_t c; + + RCC.c_r &= ~BIT(24); /* Turn off pll. */ + for(c = 0; c < TIMEOUT && RCC.c_r & BIT(25); ++ c); /* Wait for OFF. */ + + if (c == TIMEOUT) { + return E_TIMEOUT; + } + + return 0; } -inline void hse_on() +int pll_on() { - RCC.cr |= RCC_CR_HSEON; + uint32_t c; + + RCC.c_r |= BIT(24); /* Turn on PLL. */ + for(c = 0; c < TIMEOUT && !(RCC.c_r & BIT(25)); ++ c); /* Wait for RDY. */ + + if (c == TIMEOUT) { + return E_TIMEOUT; + } + + return 0; } -#define TIMER 1000000 -int set_sys_clock() +int configure_pll( + uint8_t pllp_div_factor, + pll_divisor_t pllr, /* System clock divisor. */ + pll_divisor_t pllq, /* Divison factor for PLL48M1CLK. */ + pllp_divisor_t pllp, /* Divison factor for PLLSAI2CLK. */ + uint8_t plln, /* PLL numerator. */ + pllm_divisor_t pllm, /* PLL denominator. */ + pll_src_t pllsrc /* PLL source */ ) { - uint32_t c = 0; /* Time the PLL startup. */ + if (RCC.c_r & BIT(25)) { + /* PLL must be off to configure it. */ + return E_NOT_OFF; + } - /* Turn on the HSE */ - hse_on(); + /* Make sure inputs are valid. */ + if (pllp_div_factor == 1 || pllp_div_factor > 31) { + return E_BADPLLP_DIV; + } + if (plln < 8 || plln > 86) { + return E_BADPLLN; + } - /* Wait 'til ready, or if it takes tool long, (c == TIMER). */ - for (c = 0; !is_hse_ready() && c < TIMER; ++ c); + RCC.pllcfg_r = + (pllp_div_factor << 27) | + (pllr << 24) | + (pllq << 20) | + (pllp << 16) | + (plln << 8) | + (pllm << 4) | + (pllsrc << 0); - if (c == TIMER) { - /* The HSE never came up. That's not cool! */ - return -1; - } + return 0; +} + - /* The HSE came up, now we just need to set it to be the main clock. */ - /* Don't really know why we're touching the flash registers ... */ - FLASH.acr |= FLASH_ACR_ACC64; /* Enable 64-bit access. */ - FLASH.acr |= FLASH_ACR_PRFTEN; /* Enable prefetch buffer. */ - FLASH.acr |= FLASH_ACR_LATENCY; /* Flash 1 wait state. */ +int set_sys_clock_to_hsi() +{ + /* Turn on the HSI, and wait for it to come up. */ + RCC.c_r |= BIT(8); + while(RCC.c_r & BIT(9)); - RCC.apb1enr |= RCC_APB1ENR_PWREN; /* Enable power. */ - PWR.cr = PWR_CR_VOS_0; /* Set voltage to 1.8v. */ + /* Use the HSI. */ + RCC.cfg_r |= BIT(0); + return 0; +} - /* Wait for the vwoltage regulator to turn on. */ - for (c = 0; (PWR.csr & PWR_CSR_VOSF) && c < TIMER; ++ c); +int set_sys_clock_to_pll() +{ + RCC.c_r &= ~BIT(24); /* set PLL to OFF. */ - if (c == TIMER) { - /* Timeout occurred. */ - return -2; - } + RCC.pllcfg_r = + BIT(24) | /* Enable PLLR. This is for system clock output. */ + /* Set PLLM to 2 and PLLN to 10. This gives us a 10/2 multiplier. */ + (10 << 8) | /* Set PLLN to 10. */ + (0 << 4) | /* Set PLLM to 2. */ + /* Set the input to be HSI16. */ + BIT(1); - RCC.cfgr |= RCC_CFGR_HPRE_DIV1; /* HCLK = SYSCLK/1. */ - RCC.cfgr |= RCC_CFGR_PPRE2_DIV1; /* PCLK2 = HCLK/1 */ - RCC.cfgr |= RCC_CFGR_PPRE1_DIV1; /* PCLK1 = HCLK/1 */ - /* PLL Configuration */ - RCC.cfgr &= ~( - RCC_CFGR_PLLSRC | - RCC_CFGR_PLLMUL | - RCC_CFGR_PLLDIV ); + RCC.c_r |= BIT(24); /* Turn PLL on. */ + while(!(RCC.c_r & BIT(25))); /* Wait for PLL to be ready. */ - RCC.cfgr |= - RCC_CFGR_PLLSRC_HSE | - RCC_CFGR_PLLMUL8 | - RCC_CFGR_PLLDIV2; + /* Configure the flash to have 4 wait states. This is required at + * 80 MHz. */ + FLASH.ac_r &= ~0x07; + FLASH.ac_r |= 0x04; - /* Enable the PLL. */ - RCC.cr |= RCC_CR_PLLON; + /* Set the PLL as the system clock. */ + RCC.cfg_r = 0x3; +} - /* Wait for PLL to become ready. */ - for(c = 0; !(RCC.cr & RCC_CR_PLLRDY) && c < TIMER; ++ c); +int set_system_clock_MHz(uint8_t mhz) +{ + /* Set the source of the system colck to MSI temporarily. */ + set_system_clock_src(SYSTEM_CLOCK_SRC_MSI); - if (c == TIMER) { - /* Timeout occurred. */ - return -3; + if (mhz <= 8 || mhz > 80) { + return E_BAD_ARG; } - /* Set PLL as the system clock. */ - RCC.cfgr &= ~RCC_CFGR_SW; - RCC.cfgr |= RCC_CFGR_SW_PLL; + pll_off(); - /* Wait for PLL to be used as system clock. */ - for (c = 0; (RCC.cfgr & RCC_CFGR_SWS) != RCC_CFGR_SW_PLL && c < TIMER; ++ c); + configure_pll( + 0 /* pllp_div_factor */, + PLL_DIVISOR_4 /* pllr: VCO / 4 = mhz MHz. */, + PLL_DIVISOR_4 /* pllq: VCO / 4 = mhz MHz */, + PLLP_DIVISOR_7 /* pllp */, - if (c == TIMER) { - /* Timeout occurred. */ - return -4; - } + /* The following set the frequency of VCO to (mhz*4)MHz: mhz * 1 * 4MHz. */ + mhz /* plln | mhz */, + PLLM_DIVISOR_1 /* pllm | 01 */, + PLL_SRC_MSI /* pll src | 04 Mhz */); + + pll_on(); + + /* Configure the flash to have 4 wait states. This is required at + * 80 MHz. */ + FLASH.ac_r &= ~0x07; + FLASH.ac_r |= 0x04; + /* Set the source of the system colck to PLL. */ + set_system_clock_src(SYSTEM_CLOCK_SRC_PLL); return 0; } + +int set_system_clock_src(system_clock_src_t src) +{ + uint8_t value = RCC.cfg_r & ~0x03; + RCC.cfg_r = value | src; +} |