1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
|
#include "test_harness.h"
#include "arch/stm32l4xxx/peripherals/irq.h"
#include "arch/stm32l4xxx/peripherals/nvic.h"
TEST(irq, nvic)
{
interrupt_set_t is = { 0 };
interrupt_set_add(&is, IRQ_USART2);
interrupt_set_add(&is, IRQ_USART3);
enable_interrupts(&is);
ASSERT_EQ(is.irqs[1], 0xC0);
ASSERT_EQ(NVIC.ise_r[1], 0xC0);
return 0;
}
TEST(irq, nvic_edgecase)
{
interrupt_set_t is = { 0 };
interrupt_set_add(&is, IRQ_WWDG_IRQ);
interrupt_set_add(&is, IRQ_I2C1_ER);
enable_interrupts(&is);
ASSERT_EQ(is.irqs[0], 1);
ASSERT_EQ(NVIC.ise_r[0], 1);
ASSERT_EQ(is.irqs[1], 1);
ASSERT_EQ(NVIC.ise_r[1], 1);
return 0;
}
TEST(irq, enable_single_interrupt)
{
enable_interrupt(IRQ_USART2);
ASSERT_EQ(NVIC.ise_r[1], 0x40);
return 0;
}
|
