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-rw-r--r--03-refactor/Makefile.preamble21
-rwxr-xr-x03-refactor/genmake.pl70
-rw-r--r--03-refactor/include/apb.h4
-rw-r--r--03-refactor/include/clock.h112
-rw-r--r--03-refactor/include/common.h30
-rw-r--r--03-refactor/include/delay.h12
-rw-r--r--03-refactor/include/flash.h20
-rw-r--r--03-refactor/include/gpio.h146
-rw-r--r--03-refactor/include/isr_vector.h20
-rw-r--r--03-refactor/include/printf.h15
-rw-r--r--03-refactor/include/rcc.h181
-rw-r--r--03-refactor/include/spin.h15
-rw-r--r--03-refactor/include/usart.h219
-rw-r--r--03-refactor/linker/linker_script.ld36
-rw-r--r--03-refactor/src/clock.c131
-rw-r--r--03-refactor/src/delay.c9
-rw-r--r--03-refactor/src/gpio.c52
-rw-r--r--03-refactor/src/isr_vector.c275
-rw-r--r--03-refactor/src/main.c103
-rw-r--r--03-refactor/src/printf.c152
-rw-r--r--03-refactor/src/spin.c49
-rw-r--r--03-refactor/src/usart.c131
-rw-r--r--03-refactor/src/vector.c0
23 files changed, 0 insertions, 1803 deletions
diff --git a/03-refactor/Makefile.preamble b/03-refactor/Makefile.preamble
deleted file mode 100644
index 3c8a61b..0000000
--- a/03-refactor/Makefile.preamble
+++ /dev/null
@@ -1,21 +0,0 @@
-OPT?=-O
-PREFIX?=arm-unknown-eabi-
-CC=$(PREFIX)gcc
-LD=$(PREFIX)ld
-CFLAGS?=$(OPT) -mcpu=cortex-m4 -mthumb -g -lgcc -static -nostartfiles -Iinclude
-LD_FLAGS?=-T linker/linker_script.ld -nostdlib --cref -Map linker/main.map -static
-
-
-all: _$(PREFIX)_obs/main.elf
-
-_$(PREFIX)_obs/main.bin: _$(PREFIX)_obs/main.elf
- $(PREFIX)objcopy -O binary _$(PREFIX)_obs/main.elf _$(PREFIX)_obs/main.bin
-
-flash: _$(PREFIX)_obs/main.bin
- st-flash write _$(PREFIX)_obs/main.bin 0x8000000
-
-clean:
- rm -rf _*_obs
-
-genmake:
- ./genmake.pl > Makefile
diff --git a/03-refactor/genmake.pl b/03-refactor/genmake.pl
deleted file mode 100755
index 341db3d..0000000
--- a/03-refactor/genmake.pl
+++ /dev/null
@@ -1,70 +0,0 @@
-#!/usr/bin/perl
-
-# This script is designed to introspect C files and generate a makefile to use.
-
-sub header_deps {
- my $file = @_[0];
- my @headers;
-
- if (open(my $fh, '<:encoding(UTF-8)', $file)) {
- print STDERR "\x1b[35m[Trace] - Reading file $file\x1b[00m\n";
- push(@headers, $file);
-
- while (<$fh>) {
- /#include\s+"(.*)"\s*$/ && push(@headers, header_deps("include/$1"));
- }
- }
-
- return @headers;
-}
-
-my @files = glob('src/*.c');
-my @obj_files;
-
-open(my $fh, '<:encoding(UTF-8)', "Makefile.preamble")
- or die "Missing Makefile.preamble";
-
-while (<$fh>) {
- print "$_";
-}
-
-# Emit a rule that will rerun genmake if the c files do not match.
-my $idempotency_cmd =
- "ls src/*.c include/*.h| sha1sum | awk '{print \$1}'";
-
-my $idempotency_cmd_make =
- "ls src/*.c include/*.h | sha1sum | awk '{print \$\$1}'";
-
-print "IDEMPOTENCY_HASH=" . `$idempotency_cmd` . "\n";
-
-my $arch_obs_dir = "_\$(PREFIX)_obs";
-print "CHEAT_PRE_MAKE := \$(shell mkdir -p $arch_obs_dir)\n";
-
-foreach $file (@files) {
- my $c_file = $file;
- (my $file_no_ext = $file) =~ s/src\/(.*)\.c$/\1/g;
-
- my $obj_file = "$arch_obs_dir/${file_no_ext}.o";
- my $s_file = "${file_no_ext}.s";
-
- push(@obj_files, $obj_file);
- my @deps = header_deps($c_file);
-
- my $deps_as_join = join(" ", @deps);
-
- # Emit the rule to make the object file.
- print "$obj_file: $deps_as_join\n\t";
- print '$(CC) -c ' . $c_file . ' -o ' . $obj_file . ' $(CFLAGS)' . "\n\n";
-
- # Emit the rule to make the assembly file.
- print "$s_file: $deps_as_join\n\t";
- print '$(CC) -S ' . $c_file . ' -o ' . $s_file . ' $(CFLAGS)' . "\n\n";
-}
-
-my $obj_files_deps = join(' ', @obj_files);
-print "FORCE:\n\t\n\n";
-print "$arch_obs_dir/main.elf: FORCE $obj_files_deps linker/linker_script.ld\n\t";
-print "([ \"\$\$($idempotency_cmd_make)\" != \"\$(IDEMPOTENCY_HASH)\" ] "
- . "&& ./genmake.pl > Makefile && make main.elf ) "
- . "|| "
- . "\$(LD) -o $arch_obs_dir/main.elf \$(LD_FLAGS) $obj_files_deps\n\n";
diff --git a/03-refactor/include/apb.h b/03-refactor/include/apb.h
deleted file mode 100644
index 11fa7ab..0000000
--- a/03-refactor/include/apb.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef H__APB_
-#define H__APB_
-
-#endif /* H__APB_ */
diff --git a/03-refactor/include/clock.h b/03-refactor/include/clock.h
deleted file mode 100644
index 30c1302..0000000
--- a/03-refactor/include/clock.h
+++ /dev/null
@@ -1,112 +0,0 @@
-#ifndef CLOCK_H__
-#define CLOCK_H__
-
-#include <stdint.h>
-#include "rcc.h"
-
-#define PERIPH_BASE ((uint32_t)0x40000000)
-#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
-#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00)
-#define PWR_BASE (PERIPH_BASE + 0x7000)
-#define PWR_CSR_VOSF ((uint16_t)0x0010) /*!< Voltage Scaling select flag */
-
-#ifndef __IO
-#define __IO volatile
-#endif
-
-typedef struct {
- __IO uint32_t cr;
- __IO uint32_t csr;
-} pwr_t;
-
-// typedef struct {
-// __IO uint32_t acr;
-// __IO uint32_t pecr;
-// __IO uint32_t pdkeyr;
-// __IO uint32_t pekeyr;
-// __IO uint32_t prgkeyr;
-// __IO uint32_t optkeyr;
-// __IO uint32_t sr;
-// __IO uint32_t obr;
-// __IO uint32_t wrpr;
-// } flash_t;
-
-// #define FLASH (*(flash_t*) (FLASH_R_BASE))
-#define PWR (*(pwr_t*)(PWR_BASE))
-
-/* Valid values for the PLLR/PLLQ bits of the PLLCFG register. */
-typedef enum {
- PLL_DIVISOR_2 = 1,
- PLL_DIVISOR_4 = 3,
- PLL_DIVISOR_6 = 5,
- PLL_DIVISOR_8 = 7,
- PLL_DIVISOR_OFF = 0,
-} pll_divisor_t;
-
-/* Valid values for the PLLP bits off the PLLCFG register. */
-typedef enum {
- PLLP_DIVISOR_7 = 1,
- PLLP_DIVISOR_17 = 3,
- PLLP_DIVISOR_OFF = 0,
-} pllp_divisor_t;
-
-/* Valid values for the PLLM bits of the PLLCFG register. */
-typedef enum {
- PLLM_DIVISOR_1 = 0,
- PLLM_DIVISOR_2 = 1,
- PLLM_DIVISOR_3 = 2,
- PLLM_DIVISOR_4 = 3,
- PLLM_DIVISOR_5 = 4,
- PLLM_DIVISOR_6 = 5,
- PLLM_DIVISOR_7 = 6,
- PLLM_DIVISOR_8 = 7,
-} pllm_divisor_t;
-
-/* Valid sources for the system clock. */
-typedef enum {
- SYSTEM_CLOCK_SRC_MSI = 0,
- SYSTEM_CLOCK_SRC_HSI = 1,
- SYSTEM_CLOCK_SRC_HSE = 2,
- SYSTEM_CLOCK_SRC_PLL = 3,
-} system_clock_src_t;
-
-#define E_BADPLLN (-2)
-#define E_BADPLLP_DIV (-1)
-#define E_TIMEOUT (-3)
-#define E_NOT_OFF (-4)
-#define E_BAD_ARG (-5)
-
-int enable_hsi(__IO rcc_t* rcc, bool enable);
-
-/*
- * Sets the system clock to a full 80Mhz.
- */
-int set_system_clock_MHz(uint8_t mhz);
-
-/*
- * Set the PLL on.
- */
-int pll_on();
-
-/*
- * Set the PLL off.
- */
-int pll_off();
-
-/*
- * Sets the source of the system clock.
- */
-int set_system_clock_src(system_clock_src_t src);
-
-/*
- * Configure the PLL.
- */
-int configure_pll(
- uint8_t pllp_div_factor, pll_divisor_t pllr, /* System clock divisor. */
- pll_divisor_t pllq, /* Divison factor for PLL48M1CLK. */
- pllp_divisor_t pllp, /* Divison factor for PLLSAI2CLK. */
- uint8_t plln, /* PLL numerator. */
- pllm_divisor_t pllm, /* PLL denominator. */
- pll_src_t pllsrc /* PLL source */);
-
-#endif /* CLOCK_H__ */
diff --git a/03-refactor/include/common.h b/03-refactor/include/common.h
deleted file mode 100644
index 9d5c7cd..0000000
--- a/03-refactor/include/common.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef COMMON__H
-#define COMMON__H
-
-#include <stdint.h>
-
-/* Define __IO to be volatile if it's not already. */
-#ifndef __IO
-#define __IO volatile
-#endif
-
-#define bool int
-#ifndef __cplusplus
-#define true 1
-#define false 0
-#endif
-
-#define PACKED __attribute__((packed))
-#define BIT(n) (1 << (n))
-
-#define RESERVED_CONCAT_IMPL(x, y) x ## y
-#define RESERVED_MACRO_CONCAT(x, y) RESERVED_CONCAT_IMPL(x, y)
-#define RESERVED(n) \
- bits_t RESERVED_MACRO_CONCAT(_r, __COUNTER__) :n
-
-#define RESERVE(type) \
- __IO type RESERVED_MACRO_CONCAT(_r, __COUNTER__)
-
-typedef uint32_t bits_t;
-
-#endif /* COMMON_H */
diff --git a/03-refactor/include/delay.h b/03-refactor/include/delay.h
deleted file mode 100644
index 65a26d6..0000000
--- a/03-refactor/include/delay.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef H__DELAY__
-#define H__DELAY__
-
-#include <stdint.h>
-
-/*
- * Loops and count-downs the delay, the time this takes depends on the speed
- * of the clock.
- */
-void delay(uint32_t delay);
-
-#endif /* H__DELAY__ */
diff --git a/03-refactor/include/flash.h b/03-refactor/include/flash.h
deleted file mode 100644
index a163a25..0000000
--- a/03-refactor/include/flash.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef H__FLASH_
-#define H__FLASH_
-
-#include "common.h"
-
-/*
- * Header file for dealing with flash.
- */
-
-#define FLASH_BASE 0x40022000
-
-typedef struct {
- __IO uint32_t ac_r; /* Flash access control register. */
-
- /* TODO fill out the rest. */
-} PACKED flash_t;
-
-#define FLASH (*(__IO flash_t*)FLASH_BASE)
-
-#endif /* H__FLASH_ */
diff --git a/03-refactor/include/gpio.h b/03-refactor/include/gpio.h
deleted file mode 100644
index 62169c6..0000000
--- a/03-refactor/include/gpio.h
+++ /dev/null
@@ -1,146 +0,0 @@
-#ifndef GPIO_H__
-#define GPIO_H__
-
-#include "common.h"
-#include "rcc.h"
-
-#include <stdint.h>
-
-/*
- * Possible GPIO ports.
- */
-typedef enum {
- GPIO_PORT_A = 0,
- GPIO_PORT_B = 1,
- GPIO_PORT_C = 2,
- GPIO_PORT_D = 3
-} gpio_port_number_t;
-
-/*
- * Structure defining the layout of the layout of the GPIO registers on the
- * stm32l432 development board.
- */
-typedef struct GPIO_PORT_STR {
- __IO uint32_t mode_r; /* Mode register */
- __IO uint32_t otype_r;
- __IO uint32_t ospeed_r;
- __IO uint32_t pupd_r;
- __IO uint32_t id_r;
- __IO uint32_t output_r;
- __IO uint32_t bsr_r;
- __IO uint32_t lck_r;
- __IO uint32_t af_rl;
- __IO uint32_t af_rh;
-} PACKED gpio_port_t;
-
-/*
- * Enum defining the PINs in a GPIO port. Each port has 16 pins to use in
- * the stm32l432.
- */
-typedef enum GPIO_PIN_ENUM {
- PIN_0 = 0,
- PIN_1 = 1,
- PIN_2 = 2,
- PIN_3 = 3,
- PIN_4 = 4,
- PIN_5 = 5,
- PIN_6 = 6,
- PIN_7 = 7,
- PIN_8 = 8,
- PIN_9 = 9,
- PIN_10 = 10,
- PIN_11 = 11,
- PIN_12 = 12,
- PIN_13 = 13,
- PIN_14 = 14,
- PIN_15 = 15
-} gpio_pin_t;
-
-/* Alternate function number. */
-typedef enum {
- AFN_0 = 0,
- AFN_1 = 1,
- AFN_2 = 2,
- AFN_3 = 3,
- AFN_4 = 4,
- AFN_5 = 5,
- AFN_6 = 6,
- AFN_7 = 7,
- AFN_8 = 8,
- AFN_9 = 9,
- AFN_10 = 10,
- AFN_11 = 11,
- AFN_12 = 12,
- AFN_13 = 13,
- AFN_14 = 14,
- AFN_15 = 15
-} alternate_function_t;
-
-/*
- * Enum defining the pin modes that are possible.
- */
-typedef enum {
- MODE_INPUT = 0,
- MODE_OUTPUT = 1,
- MODE_ALTERNATE = 2,
- MODE_ANALOG = 3
-} gpio_pin_mode_t;
-
-/*
- * Enum defining the pin speeds that are possible.
- */
-typedef enum {
- SPEED_2MHZ = 0,
- SPEED_10MHZ = 1,
- SPEED_50MHZ = 3,
-} speed_t;
-
-/*
- * Structure defining an OUTPUT pin. Structurally equivalent to the input pin,
- * but can be used in a slightly type-safe manner.
- */
-typedef struct {
- __IO gpio_port_t* gpio_port;
- gpio_pin_t pin;
-} gpio_output_pin_t;
-
-/*
- * Sets the mode on a GPIO pin.
- *
- * gpio_port: the gpio port to use.
- * pin: the pin number to set.
- * pin_mode: the mode to set the pin to.
- */
-void set_gpio_pin_mode(
- __IO gpio_port_t* gpio_port, gpio_pin_t pin, gpio_pin_mode_t pin_mode);
-
-/*
- * Sets the given GPIO pin to be an output pin. Returns an output_pin struct
- * corresponding to
- */
-gpio_output_pin_t set_gpio_pin_output(
- __IO gpio_port_t* gpio_port, gpio_pin_t pin);
-
-/*
- * Sets an output pin on or off.
- *
- * pin: the pin to toggle.
- * onoff: 0 for off, non-zero of on.
- */
-void set_gpio_output_pin(gpio_output_pin_t pin, bool onoff);
-
-#define pin_on(p) set_gpio_output_pin(p, 1)
-
-#define pin_off(p) set_gpio_output_pin(p, 0)
-
-/*
- * Enables a GPIO port and returns a reference to the register definition
- * of that GPIO port.
- */
-__IO gpio_port_t* enable_gpio(gpio_port_number_t number);
-
-/* Sets the alternate function for a GPIO pin. */
-void set_gpio_alternate_function(
- __IO gpio_port_t* port, gpio_pin_t gpio_pin, alternate_function_t afn);
-
-#endif /* GPIO_H__ */
diff --git a/03-refactor/include/isr_vector.h b/03-refactor/include/isr_vector.h
deleted file mode 100644
index 3e55f52..0000000
--- a/03-refactor/include/isr_vector.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef h__ISR_VECTOR_H__
-#define h__ISR_VECTOR_H__
-
-/*
- * Include file for interrupt service routines.
- */
-
-/*
- * The interrupt service routines. These link in the function `main` as the
- * main function.
- */
-extern const void* isr_vector[];
-
-/*
- * Defines an error state. This loops forever and defines a distinct flashing
- * pattern to let the user know an unhandled ISR happened.
- */
-void unhandled_isr();
-
-#endif /* h___ISR_VECTOR_H__ */
diff --git a/03-refactor/include/printf.h b/03-refactor/include/printf.h
deleted file mode 100644
index ec3eec0..0000000
--- a/03-refactor/include/printf.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef PRINTF_H_
-#define PRINTF_H_
-
-#include <stdarg.h>
-#include <stdlib.h>
-
-typedef void(*printf_callback_t)(volatile void*, char);
-
-void printf_format(
- const char* fmt,
- printf_callback_t callback,
- volatile void* callback_closure,
- va_list lst);
-
-#endif /* PRINTF_H_ */
diff --git a/03-refactor/include/rcc.h b/03-refactor/include/rcc.h
deleted file mode 100644
index 3c55e67..0000000
--- a/03-refactor/include/rcc.h
+++ /dev/null
@@ -1,181 +0,0 @@
-#ifndef H__RCC_
-#define H__RCC_
-
-#include "common.h"
-#include <stdint.h>
-
-#define RCC_BASE ((uint32_t)0x40021000)
-
-typedef enum {
- SYS_CLK_SW_MSI,
- SYS_CLK_SW_HSI,
- SYS_CLK_SW_HSE,
- SYS_CLK_SW_PLL,
-} sys_clk_sw_t;
-
-typedef enum {
- PLL_SRC_NONE,
- PLL_SRC_MSI,
- PLL_SRC_HSI,
- PLL_SRC_HSE
-} pll_src_t;
-
-typedef struct {
- /* Clock control register. Offset 0x00. */
- union RCC_CR {
- __IO uint32_t r; /* 32 bit register. */
-
- /* Bit field for the c_r */
- struct {
- bits_t msion:1; /* Turn on teh MSI. */
- bits_t msirdy:1; /* Is the MSI ready? */
- bits_t msipllen:1; /* Enabled/disable the PLL part of MSI. */
- bits_t msirgsel:1; /* MSI clock range selection. */
- bits_t msirange:4; /* MSI range. */
-
- bits_t hsion:1; /* Enable the HSI16 clock. */
- bits_t hsikeron:1; /* Force the HSI16 ON even in stop modes. */
- bits_t hsirdy:1; /* Is the hsi ready? */
- bits_t hsiasfs:1; /* HSI automatic start from STOP. */
- RESERVED(4);
-
- bits_t hseon:1; /* Enable the HSE. */
- bits_t hserdy:1; /* Is the HSE ready? */
- bits_t hsebyp:1; /* Use an external HSE. */
- bits_t csson:1; /* Clock security system enabled. */
- RESERVED(4);
-
- bits_t pllon:1; /* Enable the main PLL. */
- bits_t pllrdy:1; /* Is the PLL ready? */
- bits_t pllsai1on:1; /* Enable the SAI1 PLL. */
- bits_t pllsai1rdy:1; /* Enable the SAI1 PLL. */
- RESERVED(4);
- } PACKED;
- } __IO c;
-
- /* Internal clock sources calibration register (RCC_ICSCR) Offset 0x04. */
- union RCC_ICSCR {
- __IO uint32_t r; /* 32 bit register. */
-
- /* Bit field for icsc_r. */
- struct {
- bits_t msical:8;
- bits_t msitrim:8;
- bits_t hsical:8;
- bits_t hsitrim:5;
-
- RESERVED(3);
- } PACKED;
- } __IO icscr;
-
-
- /* Clock configuration register. */
- union RCC_CFGR {
- __IO uint32_t r;
-
- /* Bitfields for cfg_r. */
- struct {
- sys_clk_sw_t sw:2; /* System clock switch. @see sys_clk_sw_t enum. */
- sys_clk_sw_t sws:2; /* System clock switch status. */
-
- bits_t hpre:4; /* AHB prescaler. */
- bits_t ppre:3; /* APB low-speed prescaller. */
-
- RESERVED(1);
-
- bits_t stopwuck:1; /* Wakeup from Stop and CSS backup clock selection. */
- bits_t mcosel:4; /* Microcontroller clock output. */
- bits_t mcopre:3; /* MCO prescaller. */
-
- RESERVED(1);
- } PACKED __IO;
- } __IO cfg;
-
- /* PLL Configuration register. Offset 0x0c */
- union RCC_PLLCFGR {
- __IO uint32_t r;
-
- /* Bitfields for pllcfg_r */
- struct {
- pll_src_t pllsrc:2; /* PLL input source clock. */
-
- RESERVED(2);
-
- bits_t pllm:3; /* Divisions factor for the main PLL and audio PLL */
-
- RESERVED(1);
-
- bits_t plln:7; /* main PLL multiplication factor for VCO, must be
- * on interval [8, 86] inclusive */
- RESERVED(1);
-
- bits_t pllpen:1; /* Main PLL PLLSAI1CLK output enable. */
- bits_t pllp:1; /* Main division factor for PLLP.
- * 0 = 7, 1 = 17 */
- RESERVED(2);
-
- bits_t pllqen:1; /* Main PLL PLL48M1CLK output enabled. */
- bits_t pllq:2; /* PLLQ division factor. in 2^x. */
-
- RESERVED(1);
-
- bits_t pllren:1; /* PLL PLLCLK enabled. */
- bits_t pllr:2; ; /* main pll divion factor. 2^x. */
-
- bits_t pllpdiv:5; /* PLLP division factor. 0 to be handled by PLLP. */
-
- } PACKED __IO;
- } __IO pllcfg;
-
- __IO uint32_t pllsai1cfg_r; /* PLLSAI1 configuration register. 0x10 */
-
- __IO uint32_t reserved_1; /* Not used. offset 0x14. */
-
- __IO uint32_t cie_r; /* Clock interrupt enable register. 0x18 */
- __IO uint32_t cif_r; /* Clock interrupt flag regiseter. 0x1c */
- __IO uint32_t cic_r; /* Clock interrupt clear register. 0x20 */
-
- __IO uint32_t reserved_2; /* Not used. offset 0x24. */
-
- __IO uint32_t ahb1rst_r; /* AHB Peripheral 1 reset register. 0x28 */
- __IO uint32_t ahb2rst_r; /* AHB Peripheral 2 reset register. 0x2c */
- __IO uint32_t ahb3rst_r; /* AHB Peripheral 3 reset register. 0x30 */
-
- __IO uint32_t reserved_3; /* Not used. offset 0x34. */
-
- __IO uint32_t apb1rst1_r; /* APB Peripheral reset register 1. 0x38 */
- __IO uint32_t apb1rst2_r; /* APB Peripheral reset register 2. 0x3C */
- __IO uint32_t apb2rst_r; /* APB Peripheral reset register. 0x40 */
-
- __IO uint32_t reserved_4; /* Not used. offset 0x44. */
-
- __IO uint32_t ahb1en_r; /* AHB1 Peripheral enable register. 0x48 */
- __IO uint32_t ahb2en_r; /* AHB2 Peripheral enable register. 0x4C */
- __IO uint32_t ahb3en_r; /* AHB3 Peripheral enable register. 0x50 */
-
- __IO uint32_t reserved_5; /* Not used. offset 0x54. */
-
- __IO uint32_t apb1en1_r; /* APB1 Peripheral enable register 1. 0x58 */
- __IO uint32_t apb1en2_r; /* APB1 Peripheral enable register 2. 0x5C */
- __IO uint32_t apb2en_r; /* APB2 Peripheral enable register. 0x60 */
-
- __IO uint32_t reserved_6; /* Not used. offset 0x64. */
-
- __IO uint32_t ahb1smen_r; /* 0x68 */
- __IO uint32_t ahb2smen_r; /* 0x6c */
- __IO uint32_t ahb3smen_r; /* 0x70 */
-
- __IO uint32_t reserved_7;
-
- __IO uint32_t apb1smen_r1; /* 0x78 */
- __IO uint32_t apb1smen_r2; /* 0x7c */
- __IO uint32_t apb2smen_r; /* 0x80 */
-
- __IO uint32_t reserved_8;
-
- __IO uint32_t ccip_r; /* 0x88 */
-} PACKED rcc_t;
-
-#define RCC (*(__IO rcc_t*)RCC_BASE)
-
-#endif
diff --git a/03-refactor/include/spin.h b/03-refactor/include/spin.h
deleted file mode 100644
index a23d25b..0000000
--- a/03-refactor/include/spin.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef H__SPIN_
-#define H__SPIN_
-
-#include <stdint.h>
-
-/*
- * Flash a code on the status LED.
- *
- * The flash codes a binary from MSB to LSB. A long flash is a 1, a short flash
- * is a 0. Each independent flashing is succeced by a break of 4 times that
- * of a long flash.
- */
-void spin(uint32_t base_delay, uint8_t code);
-
-#endif /* H__SPIN_ */
diff --git a/03-refactor/include/usart.h b/03-refactor/include/usart.h
deleted file mode 100644
index 265ac2d..0000000
--- a/03-refactor/include/usart.h
+++ /dev/null
@@ -1,219 +0,0 @@
-#ifndef H__USART_
-#define H__USART_
-
-#include "common.h"
-#include "rcc.h"
-
-#include <stdint.h>
-
-/*
- * Possibel USART clock sources.
- */
-typedef enum {
- USART_CLK_SRC_PLK = 0, /* Clock derived from the SysClk. */
- USART_CLK_SRC_SYSCLK = 1, /* System clock. */
- USART_CLK_SRC_HSI16 = 2, /* 16MHz oscillator. */
- USART_CLK_SRC_LSE = 3 /* Low power 32kHz clock. */
-} usart_clk_src_t;
-
-typedef struct {
- /* USART conttrol register 1. */
- union USART_CR1 {
- __IO uint32_t r;
- struct {
- bits_t ue:1; /* UART enable */
- bits_t uesm:1; /* UART enabled in stop mode. */
- bits_t re:1; /* reciever enabled. */
- bits_t te:1; /* transmitter enabled. */
- bits_t idleie:1; /* Idle interrupt enabled. */
- bits_t rxneie:1; /* RXNEIE RXNE interrupt enable. */
- bits_t tcie:1;
- bits_t txeie:1;
-
- bits_t peie:1;
- bits_t ps:1;
- bits_t pce:1;
- bits_t wake:1;
- bits_t m0:1;
- bits_t mme:1;
- bits_t cmie:1;
- bits_t over8:1;
-
- bits_t dedt:5;
- bits_t deat:5;
-
- bits_t rtoie:1;
- bits_t eobie:1;
- bits_t m1:1;
- bits_t reserved:3;
- } PACKED;
- } __IO c1;
-
- /* USART control register 2. */
- union USART_CR2 {
- __IO uint32_t r;
-
- struct {
- RESERVED(4);
- bits_t addm7:1;
- bits_t lbdl:1;
- bits_t lbdie:1;
- RESERVED(1);
-
- bits_t lbcl:1;
- bits_t cpha:1;
- bits_t cpol:1;
- bits_t clken:1;
- bits_t stop:2;
- bits_t linen:1;
- bits_t swap:1;
-
- bits_t rxinv:1;
- bits_t txinv:1;
- bits_t datainv:1;
- bits_t msbfirst:1;
- bits_t abren:1;
- bits_t abrmod:2;
- bits_t rtoen:1;
-
- bits_t add:8;
- } PACKED;
- } __IO c2;
-
- union USART_CR3 {
- __IO uint32_t r;
-
- struct {
- bits_t eie:1;
- bits_t iren:1;
- bits_t irlp:1;
- bits_t hdsel:1;
- bits_t nack:1;
- bits_t scen:1;
- bits_t dmar:1;
- bits_t dmat:1;
-
- bits_t rtse:1;
- bits_t ctse:1;
- bits_t ctsie:1;
- bits_t onebit:1;
- bits_t ovrdis:1;
- bits_t ddre:1;
- bits_t dem:1;
- bits_t dep:1;
-
- RESERVED(1);
- bits_t scarcnt:3;
- bits_t wus:2;
- bits_t wufie:1;
- bits_t ucesm:1;
-
- bits_t tcbgtie:1;
- RESERVED(7);
- } PACKED;
- } __IO c3;
-
- /* USART baud rate register. */
- union USART_BRR {
- __IO uint32_t r;
-
- struct {
- uint16_t v;
- RESERVED(16);
- } PACKED;
-
- /* Structure to use when OVER8 is set in the control register
- * USART_C1. */
- struct {
- bits_t low:3;
-
- RESERVED(1);
-
- bits_t high:12;
-
- RESERVED(16);
- } PACKED over8;
- } __IO br;
-
- uint32_t gtp_r;
- uint32_t rto_r;
- uint32_t rq_r;
- uint32_t is_r;
- uint32_t ic_r;
- uint32_t rd_r;
- uint32_t td_r;
-} usart_t;
-
-#define USART1 (* (__IO usart_t*) 0x40013800)
-#define USART2 (* (__IO usart_t*) 0x40004400)
-typedef enum {
- OVERSAMPLE_8,
- OVERSAMPLE_16
-} oversampling_mode_t;
-
-static inline void usart_set_divisor(
- __IO usart_t* usart,
- uint16_t usartdiv)
-{
- if (usart->c1.r & (1 << 15)) {
- /* OVER8 is set. */
- usart->br.over8.high = (usartdiv & ~7);
- usart->br.over8.low = ((usartdiv & 7) >> 1);
- } else {
- /* OVER8 is not set. */
- usart->br.v = usartdiv;
- }
-}
-
-static inline void usart_set_oversampling_mode(
- __IO usart_t* usart,
- oversampling_mode_t mode)
-{
- usart->c1.over8 = mode == OVERSAMPLE_8;
-}
-
-typedef enum {
- USART_PARITY_DISABLED = 0,
- USART_PARITY_ODD = 1,
- USART_PARITY_EVEN = 2,
-} usart_parity_t;
-
-typedef enum {
- USART_ENABLE_TX = 0x02,
- USART_ENABLE_RX = 0x01,
- USART_ENABLE_DISABLED = 0x00,
-} usart_enable_t;
-
-void usart_set_parity(__IO usart_t* usart, usart_parity_t parity);
-
-void usart_set_enabled(__IO usart_t* usart, usart_enable_t enabled);
-
-/*
- * Send a byte on the usart, This command blocks until the data
- * is fully sent.
- */
-void usart_transmit_byte(__IO usart_t* usart, uint8_t byte);
-
-void set_usart1_clock_src(__IO rcc_t* rcc, usart_clk_src_t usart_clk_src);
-
-void set_usart1_clock_enabled(__IO rcc_t* rcc, bool enable);
-
-void set_usart2_clock_src(__IO rcc_t* rcc, usart_clk_src_t usart_clk_src);
-
-void set_usart2_clock_enabled(__IO rcc_t* rcc, bool enable);
-
-void usart_transmit_bytes(
- __IO usart_t* usart, const uint8_t* bytes, uint32_t n);
-
-void usart_transmit_str(__IO usart_t* usart, const char* str);
-
-void usart_printf(__IO usart_t* usart, const char* fmt, ...);
-
-/* Returns non-zero if usart2 is enabled. */
-int is_usart2_enabled();
-
-/* Enable the second USART. */
-int enable_usart2(uint32_t baud);
-
-
-#endif /* H__USART_ */
diff --git a/03-refactor/linker/linker_script.ld b/03-refactor/linker/linker_script.ld
deleted file mode 100644
index 348d03b..0000000
--- a/03-refactor/linker/linker_script.ld
+++ /dev/null
@@ -1,36 +0,0 @@
-MEMORY
-{
- flash : org = 0x08000000, len = 256k
- sram1 : org = 0x20000000, len = 48k
- sram2 : org = 0x10000000, len = 16k
-}
-
-SECTIONS
-{
- /* This is where the code goes. */
- . = ORIGIN(flash);
- .text : {
- *(.vectors); /* All .vector sections go here. */
- *(.text); /* All .text sections go here. */
- } >flash
-
- .data : {
- /* Data segment as defined in the flash. */
- INIT_DATA_VALUES = LOADADDR(.data);
-
- /* Data segment where it will be in memory. */
- DATA_SEGMENT_START = .;
- *(.data);
- DATA_SEGMENT_STOP = .;
-
- /* Align by 4 so we can optimize the copier to use uint32's. */
- . = ALIGN(0x04);
- } >sram1 AT>flash
-
- BSS_START = .;
- .bss : {
- *(.bss);
- . = ALIGN(0x04);
- } > sram1
- BSS_END = .;
-}
diff --git a/03-refactor/src/clock.c b/03-refactor/src/clock.c
deleted file mode 100644
index 7256500..0000000
--- a/03-refactor/src/clock.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * This file sets the system clock to its full glory of 80Mhz
- */
-
-#include "clock.h"
-#include <stdint.h>
-#include "flash.h"
-#include "gpio.h"
-#include "spin.h"
-
-#define TIMEOUT 10000
-
-int pll_off()
-{
- uint32_t c;
-
- RCC.c.pllon = false;
- for (c = 0; c < TIMEOUT && RCC.c.pllrdy; ++c)
- ; /* Wait for OFF. */
-
- if (c == TIMEOUT) {
- return E_TIMEOUT;
- }
-
- return 0;
-}
-
-int pll_on()
-{
- uint32_t c;
-
- RCC.c.pllon = true;
- for (c = 0; c < TIMEOUT && !RCC.c.pllrdy; ++c)
- ; /* Wait for RDY. */
-
- if (c == TIMEOUT) {
- return E_TIMEOUT;
- }
-
- return 0;
-}
-
-int configure_pll(
- uint8_t pllp_div_factor, pll_divisor_t pllr, /* System clock divisor. */
- pll_divisor_t pllq, /* Divison factor for PLL48M1CLK. */
- pllp_divisor_t pllp, /* Divison factor for PLLSAI2CLK. */
- uint8_t plln, /* PLL numerator. */
- pllm_divisor_t pllm, /* PLL denominator. */
- pll_src_t pllsrc /* PLL source */)
-{
- if (RCC.c.pllrdy) {
- /* PLL must be off to configure it. */
- return E_NOT_OFF;
- }
-
- /* Make sure inputs are valid. */
- if (pllp_div_factor == 1 || pllp_div_factor > 31) {
- return E_BADPLLP_DIV;
- }
- if (plln < 8 || plln > 86) {
- return E_BADPLLN;
- }
-
- union RCC_PLLCFGR tmp;
-
- tmp.pllpdiv = pllp_div_factor;
- tmp.pllr = pllr >> 1;
- tmp.pllren = pllr & 1;
- tmp.pllp = pllp >> 1;
- tmp.pllpen = pllp & 1;
- tmp.pllq = pllq >> 1;
- tmp.pllqen = pllq & 1;
- tmp.plln = plln;
- tmp.pllm = pllm;
-
- tmp.pllsrc = pllsrc;
-
- RCC.pllcfg = tmp;
-
- return 0;
-}
-
-int set_system_clock_MHz(uint8_t mhz)
-{
- /* Set the source of the system colck to MSI temporarily. */
- set_system_clock_src(SYSTEM_CLOCK_SRC_MSI);
-
- if (mhz <= 8 || mhz > 80) {
- return E_BAD_ARG;
- }
-
- pll_off();
-
- configure_pll(
- 0,
- PLL_DIVISOR_4,
- PLL_DIVISOR_4,
- PLLP_DIVISOR_7,
- mhz,
- PLLM_DIVISOR_1,
- PLL_SRC_MSI);
-