1 files changed, 13 insertions, 27 deletions

diff --git a/fdl/ch573/spi.fdl b/fdl/ch573/spi.fdl
index bdd1e24..5ce0cfb 100644
--- a/fdl/ch573/spi.fdl
+++ b/fdl/ch573/spi.fdl
@@ -8,9 +8,8 @@ package ch573.spi {
   using ch573.common;
 
   type spi_t : struct {
-    assert_pos(0x0);
     /** SPI0 Control Mode Register */
-    reg ctrl_mod(8) : struct {
+    reg ctrl_mod(8) @0x0 : struct {
       /** SPI master/slave mode select */
       mode_slave     : bit_t;
       /** Clear FIFO/counter/interrupt flag */
@@ -48,7 +47,7 @@ package ch573.spi {
     };
 
     /** SPI0 Control Configuration Register */
-    reg ctrl_cfg(8) : struct {
+    reg ctrl_cfg(8) @0x1 : struct {
       /** DMA function enable bit */
       dma_enable     : bit_t;
       reserved(1);
@@ -65,7 +64,7 @@ package ch573.spi {
     };
 
     /** SPI0 Interrupt Enable Register */
-    reg inter_en(8) : struct {
+    reg inter_en(8) @0x2 : struct {
       /** All byte transmission completion interrupt enable bit */
       ie_cnt_end     : bit_t;
       /** Single byte transmission completion interrupt enable bit */
@@ -89,13 +88,11 @@ package ch573.spi {
       reg slave_pre(8);
     };
 
-    assert_pos(0x04);
     /** SPI0 Data Buffer Register */
-    reg data_buf(8);
+    reg data_buf(8) @0x04;
 
-    assert_pos(0x05);
     /** SPI0 Status Register */
-    reg status(8) : struct {
+    reg status(8) @0x05 : struct {
       reserved(4);
       /** Command receive completion in slave mode */
       slv_cmd_act    : bit_t;
@@ -107,9 +104,8 @@ package ch573.spi {
       slv_select     : bit_t;
     };
 
-    assert_pos(0x06);
     /** SPI0 Interrupt Flag Register */
-    reg int_flag(8) : struct {
+    reg int_flag(8) @0x06 : struct {
       /** All byte transmission completion flag */
       if_cnt_end     : bit_t;
       /** Single byte transmission completion flag */
@@ -127,34 +123,24 @@ package ch573.spi {
       if_fst_byte    : bit_t;
     };
 
-    assert_pos(0x07);
     /** SPI0 FIFO Count Register */
-    reg fifo_count(8);
+    reg fifo_count(8) @0x07;
 
-    skip_to(0x0C);
     /** SPI0 Total Transmission Length Register */
-    reg total_count(16);
+    reg total_count (16) @0x0C;
 
-    skip_to(0x10);
-    reg fifo(8);
-    reserved(16);
+    reg fifo(8) @0x10;
 
-    assert_pos(0x13);
-    reg fifo_count_1(8);
+    reg fifo_count_1(8) @0x13;
 
-    assert_pos(0x14);
     /** SPI0 DMA Buffer Current Address */
-    reg dma_now(16);
-    reserved(16);
+    reg dma_now(16) @0x14;
 
-    assert_pos(0x18);
     /** SPI0 DMA Buffer Start Address */
-    reg dma_beg(16); 
-    reserved(16);
+    reg dma_beg(16) @0x18; 
 
-    assert_pos(0x1C);
     /** SPI0 DMA Buffer End Address */
-    reg dma_end(16);
+    reg dma_end(16) @0x1C;
   };
 
   instance spi0 at spi_base : spi_t;