More fields in USART and RCC set to use bitfields.

3 files changed, 39 insertions, 30 deletions

diff --git a/03-refactor/src/clock.c b/03-refactor/src/clock.c
index c4dcbac..7256500 100644
--- a/03-refactor/src/clock.c
+++ b/03-refactor/src/clock.c
@@ -61,8 +61,21 @@ int configure_pll(
     return E_BADPLLN;
   }
 
-  RCC.pllcfg_r = (pllp_div_factor << 27) | (pllr << 24) | (pllq << 20) |
-                 (pllp << 16) | (plln << 8) | (pllm << 4) | (pllsrc << 0);
+  union RCC_PLLCFGR tmp;
+
+  tmp.pllpdiv = pllp_div_factor;
+  tmp.pllr = pllr >> 1;
+  tmp.pllren = pllr & 1;
+  tmp.pllp = pllp >> 1;
+  tmp.pllpen = pllp & 1;
+  tmp.pllq = pllq >> 1;
+  tmp.pllqen = pllq & 1;
+  tmp.plln = plln;
+  tmp.pllm = pllm;
+
+  tmp.pllsrc = pllsrc;
+
+  RCC.pllcfg = tmp;
 
   return 0;
 }
@@ -79,13 +92,13 @@ int set_system_clock_MHz(uint8_t mhz)
   pll_off();
 
   configure_pll(
-      0 /* pllp_div_factor */, PLL_DIVISOR_4 /* pllr: VCO / 4 = mhz MHz. */,
-      PLL_DIVISOR_4 /* pllq: VCO / 4 = mhz MHz */, PLLP_DIVISOR_7 /* pllp */,
-
-      /* The following set the frequency of VCO to (mhz*4)MHz: mhz * 1 * 4MHz.
-       */
-      mhz /* plln    | mhz */, PLLM_DIVISOR_1 /* pllm    | 01 */,
-      PLL_SRC_MSI /* pll src | 04 Mhz */);
+      0,
+      PLL_DIVISOR_4,
+      PLL_DIVISOR_4,
+      PLLP_DIVISOR_7,
+      mhz,
+      PLLM_DIVISOR_1,
+      PLL_SRC_MSI);
 
   pll_on();
 
@@ -101,8 +114,8 @@ int set_system_clock_MHz(uint8_t mhz)
 
 int set_system_clock_src(system_clock_src_t src)
 {
-  uint8_t value = RCC.cfg_r & ~0x03;
-  RCC.cfg_r = value | src;
+  uint8_t value = RCC.cfg.r & ~0x03;
+  RCC.cfg.r = value | src;
 }
 
 int enable_hsi(__IO rcc_t* rcc, bool enable)
diff --git a/03-refactor/src/main.c b/03-refactor/src/main.c
index 5af52ed..0545087 100644
--- a/03-refactor/src/main.c
+++ b/03-refactor/src/main.c
@@ -30,9 +30,9 @@ int enable_usart2(uint32_t baud_rate)
   // disable USART first to allow setting of other control bits
   // This also disables parity checking and enables 16 times oversampling
 
-  USART2.c_r1 = 0;
-  USART2.c_r2 = 0;
-  USART2.c_r3 = 0;
+  USART2.c1.r = 0;
+  USART2.c2.r = 0;
+  USART2.c3.r = 0;
 
   usart_set_divisor(&USART2, 16000000 / baud_rate);
   usart_set_enabled(&USART2, USART_ENABLE_TX | USART_ENABLE_RX);
@@ -60,13 +60,13 @@ int enable_usart1(uint32_t baud_rate)
   RCC.apb2rst_r &= ~BIT(14); /* De-assert reset of USART1 */
 
   uint32_t baud_rate_div = 80000000 / baud_rate;
-  USART1.c_r1 = 0;
-  USART1.c_r2 = 0;
-  USART1.c_r3 = 0;
-  USART1.br_r = baud_rate_div;
+  USART1.c1.r = 0;
+  USART1.c2.r = 0;
+  USART1.c3.r = 0;
+  USART1.br.v = baud_rate_div;
 
-  USART1.c_r1 |= BIT(3) | BIT(2);
-  USART1.c_r1 |= BIT(0);
+  USART1.c1.r |= BIT(3) | BIT(2);
+  USART1.c1.r |= BIT(0);
 
   /* Enable the transmitter and the receiver. */
   usart_set_enabled(&USART1, USART_ENABLE_TX);
diff --git a/03-refactor/src/usart.c b/03-refactor/src/usart.c
index eddfbe7..a3b0061 100644
--- a/03-refactor/src/usart.c
+++ b/03-refactor/src/usart.c
@@ -31,23 +31,19 @@ void set_usart1_clock_enabled(__IO rcc_t* rcc, bool enable)
 
 void usart_set_parity(__IO usart_t* usart, usart_parity_t parity)
 {
-  uint32_t c_r1 = usart->c_r1;
-  c_r1 &= ~(0x3 << 9);
-  c_r1 |= parity;
-  usart->c_r1 = c_r1;
+  usart->c1.pce = !!parity;
+  usart->c1.ps  = parity & 1;
 }
 
 void usart_set_enabled(__IO usart_t* usart, usart_enable_t enabled)
 {
-  uint32_t c_r1 = usart->c_r1;
-
   if (!enabled) {
-    usart->c1_bf.ue = 0;
+    usart->c1.ue = 0;
   } else {
     /* Set the rx enabled. */
-    usart->c1_bf.re = !!(enabled & USART_ENABLE_RX);
-    usart->c1_bf.te = !!(enabled & USART_ENABLE_TX);
-    usart->c1_bf.ue = 1;
+    usart->c1.re = !!(enabled & USART_ENABLE_RX);
+    usart->c1.te = !!(enabled & USART_ENABLE_TX);
+    usart->c1.ue = 1;
   }
 }