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authorJosh Rahm <joshuarahm@gmail.com>2022-12-28 13:50:47 -0700
committerJosh Rahm <joshuarahm@gmail.com>2022-12-28 13:50:47 -0700
commit9acc760308079ae553f4b47694a5682da99bf2a3 (patch)
tree747d65d1faee5551fd001a85fe8858b0da908e57
parente39a5b294588dca668ea82b3e683c1684e85ca0c (diff)
downloadverilog-main.tar.gz
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verilog-main.zip
Rearchitect into separate projects.main
-rw-r--r--clock_divider/apio.ini (renamed from apio.ini)0
-rw-r--r--clock_divider/clock_divider.v (renamed from clock_divider.v)0
-rw-r--r--clock_divider/clock_divider_tb.v (renamed from clock_divider_tb.v)0
-rw-r--r--collatz/apio.ini3
-rw-r--r--collatz/collatz.v (renamed from collatz.v)25
-rw-r--r--collatz/collatz_tb.v (renamed from collatz_tb.v)33
6 files changed, 32 insertions, 29 deletions
diff --git a/apio.ini b/clock_divider/apio.ini
index 1faba9f..1faba9f 100644
--- a/apio.ini
+++ b/clock_divider/apio.ini
diff --git a/clock_divider.v b/clock_divider/clock_divider.v
index 8f46aa3..8f46aa3 100644
--- a/clock_divider.v
+++ b/clock_divider/clock_divider.v
diff --git a/clock_divider_tb.v b/clock_divider/clock_divider_tb.v
index 7499454..7499454 100644
--- a/clock_divider_tb.v
+++ b/clock_divider/clock_divider_tb.v
diff --git a/collatz/apio.ini b/collatz/apio.ini
new file mode 100644
index 0000000..1faba9f
--- /dev/null
+++ b/collatz/apio.ini
@@ -0,0 +1,3 @@
+[env]
+board = icestick
+
diff --git a/collatz.v b/collatz/collatz.v
index 35550c2..e046815 100644
--- a/collatz.v
+++ b/collatz/collatz.v
@@ -5,18 +5,20 @@
* required for that number to get down to 1 using the collatz
* conjecture.
*/
-module collatz (
+module collatz #(
+ parameter integer WIDTH = 16
+) (
/* Input clock and reset pin. */
input clk,
input rst,
/* The number to calculate. */
- input wire [15:0] in_start,
+ input wire [WIDTH-1:0] in_start,
/* Pulsing the start_int pin will start the calculation. */
input wire start_int,
/* Output count. */
- output reg [15:0] o_count,
+ output reg [WIDTH-1:0] o_count,
/* Set to high when the module is idle and ready to start.
* While computing, this output is set to low.
@@ -30,11 +32,11 @@ module collatz (
localparam integer IDLE = 0;
localparam integer SPINNING = 1;
- reg state = 0; // IDLE or SPINNING
- reg [15:0] count = 0; // Current count
- reg [15:0] n = 0; // Current value
+ reg state = 0;
+ reg [WIDTH-1:0] count = 0;
+ reg [WIDTH-1:0] n = 0;
- wire is_even = ~n[0]; // Is the current value even.
+ wire is_even = ~n[0]; // Is the current value even.
assign idle = state == IDLE;
// When the start_int input is set to high, copy the in_start to the current
@@ -50,19 +52,16 @@ module collatz (
always @(posedge clk or posedge rst) begin
// On reset, reset the state.
if (rst == 1'b1) begin
+ count = 0;
state <= IDLE;
- count <= 0;
n <= 0;
- // If the state is idle, reset the count to 0.
- end else if (state == IDLE) begin
- n <= 0;
-
- // If the state is calculating, do the next step.
+ // If the state is idle, reset the count to 0.
end else if (state == SPINNING) begin
// If n is 1, then set the output and go back to the IDLE state.
if (n <= 1) begin
o_count = count;
+ n <= 0;
state = IDLE;
end else begin
// If is_even, divide by two, otherwise multiply by 3 and add 1.
diff --git a/collatz_tb.v b/collatz/collatz_tb.v
index 7419d3f..c56b13c 100644
--- a/collatz_tb.v
+++ b/collatz/collatz_tb.v
@@ -1,31 +1,32 @@
`timescale 1 ns / 10 ps
module collatz_tb ();
- reg clk = 0;
- reg rst = 0;
+ reg clk = 0;
+ reg rst = 0;
- wire finish;
+ wire idle;
- localparam integer DURATION = 10_000;
+ localparam integer DURATION = 500_000;
always begin
#41.667;
-
- clk = ~ clk;
+ clk = ~clk;
end
- reg [15:0] n = 9;
+ reg [24:0] n = 1_000_000;
reg start_int;
- wire [15:0] count_out;
-
- collatz ctz (
- .clk(clk),
- .rst(rst),
- .in_start(n),
- .start_int(start_int),
- .o_count(count_out),
- .finish_int(finish)
+ wire [24:0] count_out;
+
+ collatz #(
+ .WIDTH(32)
+ ) ctz (
+ .clk(clk),
+ .rst(rst),
+ .in_start(n),
+ .start_int(start_int),
+ .o_count(count_out),
+ .idle(idle)
);
initial begin