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author | Josh Rahm <joshuarahm@gmail.com> | 2022-12-28 13:50:47 -0700 |
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committer | Josh Rahm <joshuarahm@gmail.com> | 2022-12-28 13:50:47 -0700 |
commit | 9acc760308079ae553f4b47694a5682da99bf2a3 (patch) | |
tree | 747d65d1faee5551fd001a85fe8858b0da908e57 /clock_divider/clock_divider.v | |
parent | e39a5b294588dca668ea82b3e683c1684e85ca0c (diff) | |
download | verilog-main.tar.gz verilog-main.tar.bz2 verilog-main.zip |
Rearchitect into separate projects.main
Diffstat (limited to 'clock_divider/clock_divider.v')
-rw-r--r-- | clock_divider/clock_divider.v | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/clock_divider/clock_divider.v b/clock_divider/clock_divider.v new file mode 100644 index 0000000..8f46aa3 --- /dev/null +++ b/clock_divider/clock_divider.v @@ -0,0 +1,25 @@ +module clock_divider #( + parameter integer COUNT_WIDTH = 24, + parameter [COUNT_WIDTH:0] MAX_COUNT = 6000000 +) ( + input clk, + input rst, + + output reg div_clk +); + + reg [COUNT_WIDTH:0] count = 0; + + always @(posedge clk or posedge rst) begin + if (rst == 1'b1) begin + count <= 0; + div_clk <= 0; + end else if (count == MAX_COUNT - 1) begin + count <= 0; + div_clk <= ~div_clk; + end else begin + count <= count + 1; + end + end + +endmodule |