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authorJosh Rahm <joshuarahm@gmail.com>2022-12-28 13:50:47 -0700
committerJosh Rahm <joshuarahm@gmail.com>2022-12-28 13:50:47 -0700
commit9acc760308079ae553f4b47694a5682da99bf2a3 (patch)
tree747d65d1faee5551fd001a85fe8858b0da908e57 /clock_divider/clock_divider_tb.v
parente39a5b294588dca668ea82b3e683c1684e85ca0c (diff)
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Diffstat (limited to 'clock_divider/clock_divider_tb.v')
-rw-r--r--clock_divider/clock_divider_tb.v55
1 files changed, 55 insertions, 0 deletions
diff --git a/clock_divider/clock_divider_tb.v b/clock_divider/clock_divider_tb.v
new file mode 100644
index 0000000..7499454
--- /dev/null
+++ b/clock_divider/clock_divider_tb.v
@@ -0,0 +1,55 @@
+`timescale 1 ns / 10 ps
+
+module clock_divider_tb ();
+
+ reg clk = 0;
+ reg rst = 0;
+
+ wire out;
+ wire out2;
+
+ // Simulation time: 10_000 * 1 ns = 10 μs.
+ localparam integer DURATION = 10_000;
+
+ // generate clock signal : 1 / ((2 * 41.67) * 1 ns) == 11,999,040.08 MHz
+ always begin
+ // Delay for 41.667
+ #41.667;
+
+ clk = ~clk;
+ end
+
+ clock_divider #(
+ .COUNT_WIDTH(4),
+ .MAX_COUNT (4)
+ ) utt (
+ .clk(clk),
+ .rst(rst),
+ .div_clk(out)
+ );
+
+ clock_divider #(
+ .COUNT_WIDTH(4),
+ .MAX_COUNT (4)
+ ) utt2 (
+ .clk(out),
+ .rst(rst),
+ .div_clk(out2)
+ );
+
+ initial begin
+ #10 rst = 1'b1;
+ #1 rst = 1'b0;
+ end
+
+ initial begin
+ $dumpfile("clock_divider_tb.vcd");
+ $dumpvars(0, clock_divider_tb);
+
+ #(DURATION);
+ $display("Finished!");
+ $finish;
+ end
+
+endmodule
+