3 files changed, 83 insertions, 0 deletions
diff --git a/clock_divider/apio.ini b/clock_divider/apio.ini
new file mode 100644
index 0000000..1faba9f
--- /dev/null
+++ b/clock_divider/apio.ini
@@ -0,0 +1,3 @@
+[env]
+board = icestick
+
diff --git a/clock_divider/clock_divider.v b/clock_divider/clock_divider.v
new file mode 100644
index 0000000..8f46aa3
--- /dev/null
+++ b/clock_divider/clock_divider.v
@@ -0,0 +1,25 @@
+module clock_divider #(
+    parameter integer COUNT_WIDTH = 24,
+    parameter [COUNT_WIDTH:0] MAX_COUNT = 6000000
+) (
+    input clk,
+    input rst,
+
+    output reg div_clk
+);
+
+  reg [COUNT_WIDTH:0] count = 0;
+
+  always @(posedge clk or posedge rst) begin
+    if (rst == 1'b1) begin
+      count   <= 0;
+      div_clk <= 0;
+    end else if (count == MAX_COUNT - 1) begin
+      count   <= 0;
+      div_clk <= ~div_clk;
+    end else begin
+      count <= count + 1;
+    end
+  end
+
+endmodule
diff --git a/clock_divider/clock_divider_tb.v b/clock_divider/clock_divider_tb.v
new file mode 100644
index 0000000..7499454
--- /dev/null
+++ b/clock_divider/clock_divider_tb.v
@@ -0,0 +1,55 @@
+`timescale 1 ns / 10 ps
+
+module clock_divider_tb ();
+
+  reg  clk = 0;
+  reg  rst = 0;
+
+  wire out;
+  wire out2;
+
+  // Simulation time: 10_000 * 1 ns = 10 μs.
+  localparam integer DURATION = 10_000;
+
+  // generate clock signal : 1 / ((2 *  41.67) * 1 ns) == 11,999,040.08 MHz
+  always begin
+    // Delay for 41.667
+    #41.667;
+
+    clk = ~clk;
+  end
+
+  clock_divider #(
+      .COUNT_WIDTH(4),
+      .MAX_COUNT  (4)
+  ) utt (
+      .clk(clk),
+      .rst(rst),
+      .div_clk(out)
+  );
+
+  clock_divider #(
+      .COUNT_WIDTH(4),
+      .MAX_COUNT  (4)
+  ) utt2 (
+      .clk(out),
+      .rst(rst),
+      .div_clk(out2)
+  );
+
+  initial begin
+    #10 rst = 1'b1;
+    #1 rst = 1'b0;
+  end
+
+  initial begin
+    $dumpfile("clock_divider_tb.vcd");
+    $dumpvars(0, clock_divider_tb);
+
+    #(DURATION);
+    $display("Finished!");
+    $finish;
+  end
+
+endmodule
+