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verilog.git
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Happy hacking in Verilog
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path:
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/
clock_divider
Mode
Name
Size
-rw-r--r--
apio.ini
24
log
plain
blame
-rw-r--r--
clock_divider.v
486
log
plain
blame
-rw-r--r--
clock_divider_tb.v
851
log
plain
blame
